Need to delay a signal a great number of clk cycles

Discussion in 'VHDL' started by martin.wahlstedt, May 14, 2007.

  1. martin.wahlstedt

    martin.wahlstedt

    Joined:
    Mar 29, 2007
    Messages:
    14
    Hi

    Do someone have any tricks on how to delay a signal without using shift registers? Need to delay an enable signal (one bit) approx. 1024 clock cycles, and an shift register implementation will be quite big. The implementation is to be synthesises so 'after' commands are not possible.

    Thanks
    Martin
    martin.wahlstedt, May 14, 2007
    #1
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  2. martin.wahlstedt

    scottcarl

    Joined:
    May 4, 2007
    Messages:
    49
    Location:
    USA
    Use a 10-bit counter to delay something 1024 clock cycles. Use this 2-state state machine.

    Code:
    Count_grab : process(clk, reset)
    begin
      if (reset = '1') then
        counter               <= (others => '0'); -- Counts from 0 to 1023
        YOUR_END_PULSE <= '0';  
        s_pulse_grab <= s_idle;
      elsif elsif rising_edge(clk) then
           counter              <= (others => '0'); -- defualt wherever it's not defined
           YOUR_END_PULSE <= '0';   -- defualt wherever it's not defined
        when s_idle => 
          if (incoming_pulse = '1') then  -- Latch in the incoming pulse 
            counter        <= counter + '1'; -- Start counting
            s_pulse_grab <= s_enabling;
          else
            s_pulse_grab <= s_idle;
          end if;
        when s_enabling => 
          if (counter = 1022) then  -- Find one sample before the end 
            YOUR_END_PULSE <= '1';   -- This is your 1024 delayed pulse
            s_pulse_grab       <= s_idle;
          else
            counter              <= counter + '1'; 
            s_pulse_grab       <= s_enabling;
          end if;
        when others =>
      end if;
    end process;
    Enjoy,
    Scott
    Last edited: May 15, 2007
    scottcarl, May 15, 2007
    #2
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