Newbie VHDL Blocks

Discussion in 'VHDL' started by nvd, Sep 11, 2009.

  1. nvd

    nvd

    Joined:
    Sep 11, 2009
    Messages:
    1
    I am new to VHDL and want to ask some questions.

    Currently I know about the ENTITY and I know it can have many processes.

    1: If I have divided my design into many logical blocks then how can I translate those into VHDL? Should I go for ENTITIES or many processes in the same ENTITY?

    2: How can I share information between different processes and ENTITIES?

    3: What are ports for?
    nvd, Sep 11, 2009
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  2. nvd

    joris

    Joined:
    Jan 29, 2009
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    2. you probably have to use signals to make communication between processes possible; not sure whether it's smart to have multiple processes though.
    3. ports define the signals (wires) entering and leaving the entity.

    1. Both are possible, though it may be more natural to have each logical block as a separate entity.

    HTH, Joris
    joris, Sep 13, 2009
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  3. nvd

    debayan_p

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    Jun 2, 2009
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    For complex digital designs, I do something like this......


    I keep each digital block as a separate entity....they have their own clock, n_reset, input & output signals.

    Have test-benches for each of these entities to verify their proper working.

    After testing each of the blocks, I combine them under a single unit, using the "component" function of VHDL.

    This top-level unit will again have the clock, n_reset, and necessary input & output signals defined in its entity block.

    For inter-connection b/w the various blocks use common "signals" that are defined in the top-module, just after the definition of all the "components".

    I have been doing digital design with VHDL for a year now, and have found out that more process blocks within a single architecture block clutters the code ! Well there are of course exceptional cases where 4 or 5 process blocks within one architecture cannot be avoided !

    All the best
    debayan_p, Sep 15, 2009
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