One of my signals not initialising

Discussion in 'VHDL' started by maurizio.gencarelli@dsto.defence.gov.au, Apr 11, 2007.

  1. Guest

    Attached is the code I am having problem with. Signal frame_status is
    undefined instead of being initialised to "000000000" when it is all
    states except read_frame_condition and write_frame_status. For some
    reason the assignment frame_status<="000000000"; just after the begin
    statement in the OUTPUT_DECODE process is not executing despite
    certain it is following that execution path. However, if I initialise
    frame_status when I declare it ie. signal
    frame_status:STD_LOGIC_VECTOR (8 downto 0):="000000000"; and remove
    frame_status<="000000000"; from the process it works.

    Any ideas ???


    ----------------------------------------------------------------------------------
    -- Company:
    -- Engineer:
    --
    -- Create Date: 11:19:04 01/22/2007
    -- Design Name:
    -- Module Name: RX_FIFO_WR_CONTROL - Behavioral
    -- Project Name:
    -- Target Devices:
    -- Tool versions:
    -- Description:
    --
    -- Dependencies:
    --
    -- Revision:
    -- Revision 0.01 - File Created
    -- Additional Comments:
    --
    ----------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity RX_FIFO_WR_CONTROL is
    Port ( data_clk : in STD_LOGIC;
    data:in STD_LOGIC_VECTOR (7 downto 0);
    frame_mrk : in STD_LOGIC;
    rxdv: in STD_LOGIC;
    fifo_full : in STD_LOGIC;
    frame_good: in STD_LOGIC;
    frame_bad: in STD_LOGIC;
    fifo_wr_data: out STD_LOGIC_VECTOR (8 downto 0);
    wr_fifo_en : out STD_LOGIC;
    rst: IN STD_LOGIC);
    end RX_FIFO_WR_CONTROL;

    architecture RTL of RX_FIFO_WR_CONTROL is


    type FIFO_CNTRL_STATE is
    (IDLE,WRITE_FIFO,WAIT_END,READ_FRAME_CONDITION,WRITE_FRAME_STATUS);
    signal CURRENT_STATE,NEXT_STATE:FIFO_CNTRL_STATE;
    signal OVR_FLOW: std_logic;
    signal TEMP_DATA:STD_LOGIC_VECTOR (8 downto 0);
    signal frame_status:STD_LOGIC_VECTOR (8 downto 0); <-- if I
    initialise frame_status

    to "000000000" here, instead of

    frame_status<="000000000"; in

    process OUTPUT_DECODE, it works


    signal data_present:std_logic;
    signal I_am_here:std_logic_vector(3 downto 0);

    begin


    SYNC: process (data_clk,rst)
    begin
    if rising_edge(data_clk) then
    if rst='1' then
    current_state<=idle;
    data_present<='0';
    else
    current_state<=next_state;
    data_present<='1';
    end if;
    end if;
    if data_clk='1' then
    data_present<='1';
    else
    data_present<='0';
    end if;
    end process SYNC;



    OUTPUT_DECODE: process
    (current_state,frame_mrk,fifo_full,data_present,data,frame_good,frame_bad,frame_status)
    begin
    wr_fifo_en<='0';
    frame_status<="000000000"; <----- frame_status is not initialising
    here, it is undefined
    TEMP_DATA<="000000000";
    OVR_FLOW<='0';
    I_am_here<="0101";<--- This indicates it is passing this execution
    path, and it works.
    if current_state = idle and frame_mrk = '1' then
    wr_fifo_en<='1';
    TEMP_DATA(7 downto 0)<=data;
    TEMP_DATA(8)<=frame_mrk;
    end if ;
    if current_state=write_fifo and fifo_full='1' then
    OVR_FLOW<='1';
    wr_fifo_en<='0';
    else
    TEMP_DATA(8)<=frame_mrk;
    TEMP_DATA(7 downto 0)<=data;
    TEMP_DATA(8)<=frame_mrk;
    end if;
    if current_state = write_fifo and frame_mrk = '1' then
    wr_fifo_en<='1';
    end if;
    if frame_mrk='0' then
    TEMP_DATA(8)<=frame_mrk;
    wr_fifo_en<='0';
    end if;
    if current_state=wait_end and fifo_full='1' then
    OVR_FLOW<='1';
    end if;
    if current_state=read_frame_condition and rising_edge(data_present)
    then
    frame_status(8)<='0';
    frame_status(7)<=OVR_FLOW;
    frame_status(6)<=frame_good;
    frame_status(5)<=frame_bad;
    frame_status(4 downto 0)<="00000";
    else
    frame_status<=frame_status;
    end if;
    if current_state=write_frame_status then
    wr_fifo_en<='1';
    TEMP_DATA<=frame_status;
    end if;
    end process;

    fifo_wr_data<=TEMP_DATA;

    COMB: process (current_state,frame_mrk,rxdv)
    begin
    next_state<=current_state;
    case current_state is
    when idle =>
    if frame_mrk='1' then
    next_state<=write_fifo;
    end if;
    when write_fifo =>
    if frame_mrk='0' then
    next_state<= wait_end;
    end if;
    when wait_end =>
    if rxdv='0' then
    next_state<=read_frame_condition;
    end if;
    when read_frame_condition =>
    next_state<=write_frame_status;
    when write_frame_status =>
    next_state<=idle;
    when others =>
    next_state <= idle;
    end case;
    end process COMB;

    end RTL;

    Regards

    Mario Gencarelli

    Air Operations Division
    Defence Science and Technology Organisation
    Australia
    , Apr 11, 2007
    #1
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  2. Andy Guest

    On Apr 11, 2:38 am, wrote:
    > Attached is the code I am having problem with. Signal frame_status is
    > undefined instead of being initialised to "000000000" when it is all
    > states except read_frame_condition and write_frame_status. For some
    > reason the assignment frame_status<="000000000"; just after the begin
    > statement in the OUTPUT_DECODE process is not executing despite
    > certain it is following that execution path. However, if I initialise
    > frame_status when I declare it ie. signal
    > frame_status:STD_LOGIC_VECTOR (8 downto 0):="000000000"; and remove
    > frame_status<="000000000"; from the process it works.
    >
    > Any ideas ???
    >
    > ----------------------------------------------------------------------------------
    > -- Company:
    > -- Engineer:
    > --
    > -- Create Date: 11:19:04 01/22/2007
    > -- Design Name:
    > -- Module Name: RX_FIFO_WR_CONTROL - Behavioral
    > -- Project Name:
    > -- Target Devices:
    > -- Tool versions:
    > -- Description:
    > --
    > -- Dependencies:
    > --
    > -- Revision:
    > -- Revision 0.01 - File Created
    > -- Additional Comments:
    > --
    > ----------------------------------------------------------------------------------
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    >
    > ---- Uncomment the following library declaration if instantiating
    > ---- any Xilinx primitives in this code.
    > --library UNISIM;
    > --use UNISIM.VComponents.all;
    >
    > entity RX_FIFO_WR_CONTROL is
    > Port ( data_clk : in STD_LOGIC;
    > data:in STD_LOGIC_VECTOR (7 downto 0);
    > frame_mrk : in STD_LOGIC;
    > rxdv: in STD_LOGIC;
    > fifo_full : in STD_LOGIC;
    > frame_good: in STD_LOGIC;
    > frame_bad: in STD_LOGIC;
    > fifo_wr_data: out STD_LOGIC_VECTOR (8 downto 0);
    > wr_fifo_en : out STD_LOGIC;
    > rst: IN STD_LOGIC);
    > end RX_FIFO_WR_CONTROL;
    >
    > architecture RTL of RX_FIFO_WR_CONTROL is
    >
    > type FIFO_CNTRL_STATE is
    > (IDLE,WRITE_FIFO,WAIT_END,READ_FRAME_CONDITION,WRITE_FRAME_STATUS);
    > signal CURRENT_STATE,NEXT_STATE:FIFO_CNTRL_STATE;
    > signal OVR_FLOW: std_logic;
    > signal TEMP_DATA:STD_LOGIC_VECTOR (8 downto 0);
    > signal frame_status:STD_LOGIC_VECTOR (8 downto 0); <-- if I
    > initialise frame_status
    >
    > to "000000000" here, instead of
    >
    > frame_status<="000000000"; in
    >
    > process OUTPUT_DECODE, it works
    >
    > signal data_present:std_logic;
    > signal I_am_here:std_logic_vector(3 downto 0);
    >
    > begin
    >
    > SYNC: process (data_clk,rst)
    > begin
    > if rising_edge(data_clk) then
    > if rst='1' then
    > current_state<=idle;
    > data_present<='0';
    > else
    > current_state<=next_state;
    > data_present<='1';
    > end if;
    > end if;
    > if data_clk='1' then
    > data_present<='1';
    > else
    > data_present<='0';
    > end if;
    > end process SYNC;
    >
    > OUTPUT_DECODE: process
    > (current_state,frame_mrk,fifo_full,data_present,data,frame_good,frame_bad,frame_status)
    > begin
    > wr_fifo_en<='0';
    > frame_status<="000000000"; <----- frame_status is not initialising
    > here, it is undefined
    > TEMP_DATA<="000000000";
    > OVR_FLOW<='0';
    > I_am_here<="0101";<--- This indicates it is passing this execution
    > path, and it works.
    > if current_state = idle and frame_mrk = '1' then
    > wr_fifo_en<='1';
    > TEMP_DATA(7 downto 0)<=data;
    > TEMP_DATA(8)<=frame_mrk;
    > end if ;
    > if current_state=write_fifo and fifo_full='1' then
    > OVR_FLOW<='1';
    > wr_fifo_en<='0';
    > else
    > TEMP_DATA(8)<=frame_mrk;
    > TEMP_DATA(7 downto 0)<=data;
    > TEMP_DATA(8)<=frame_mrk;
    > end if;
    > if current_state = write_fifo and frame_mrk = '1' then
    > wr_fifo_en<='1';
    > end if;
    > if frame_mrk='0' then
    > TEMP_DATA(8)<=frame_mrk;
    > wr_fifo_en<='0';
    > end if;
    > if current_state=wait_end and fifo_full='1' then
    > OVR_FLOW<='1';
    > end if;
    > if current_state=read_frame_condition and rising_edge(data_present)
    > then
    > frame_status(8)<='0';
    > frame_status(7)<=OVR_FLOW;
    > frame_status(6)<=frame_good;
    > frame_status(5)<=frame_bad;
    > frame_status(4 downto 0)<="00000";
    > else
    > frame_status<=frame_status;
    > end if;
    > if current_state=write_frame_status then
    > wr_fifo_en<='1';
    > TEMP_DATA<=frame_status;
    > end if;
    > end process;
    >
    > fifo_wr_data<=TEMP_DATA;
    >
    > COMB: process (current_state,frame_mrk,rxdv)
    > begin
    > next_state<=current_state;
    > case current_state is
    > when idle =>
    > if frame_mrk='1' then
    > next_state<=write_fifo;
    > end if;
    > when write_fifo =>
    > if frame_mrk='0' then
    > next_state<= wait_end;
    > end if;
    > when wait_end =>
    > if rxdv='0' then
    > next_state<=read_frame_condition;
    > end if;
    > when read_frame_condition =>
    > next_state<=write_frame_status;
    > when write_frame_status =>
    > next_state<=idle;
    > when others =>
    > next_state <= idle;
    > end case;
    > end process COMB;
    >
    > end RTL;
    >
    > Regards
    >
    > Mario Gencarelli
    >
    > Air Operations Division
    > Defence Science and Technology Organisation
    > Australia


    I'm not sure exactly why the code is not behaving the way you want it
    to, but if you intend this to be synthesizable, then the resulting
    hardware (if any) certainly won't behave the way you want.

    You cannot mix clocked functionality in a combinatorial process. The
    conditional assignment to frame_status depends on a rising edge
    condition, which would normally infer a register, but this is inside a
    combinatorial process. That won't work.

    In the sync process, you also try to generate data_present
    combinatorially within a clocked process. While with certain
    limitations that kind of thing can be done with some tools, none will
    correctly implement a combinatorial path from input signal to output
    signal in a clocked process.

    finally, use one clock if at all possible. Do not use one clock to
    generate another clock, and then use that generated clock to feed data
    into registers clocked by the original clock. Even "buffered" clocks
    will cause simulation mismatches between rtl and gates due to delta
    delays in the rtl code.

    I generally prefer to code everything possible from within a clocked
    process. It is simpler to write, and there is no possibility of
    inferring a latch. Any combinatorial functionality (except complete
    combinatorial path from input to output) can be described within a
    clocked process.

    Solve these problems, and your other problem may just go away...

    Andy
    Andy, Apr 11, 2007
    #2
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