Out of range on type real?

[Brandon]

I'm trying to scale some reals in a test bench, however I'm getting an
out of range error:

<SNIP>

signal srefloat_unscale : real;
signal simfloat_unscale : real;
signal srefloat_test : real;
signal simfloat_test : real;

begin
....
....
....
scaleresult_proc: process(srefloat_unscale, simfloat_unscale)
begin
srefloat_test <= srefloat_unscale*2.0**7;
simfloat_test <= simfloat_unscale*2.0**7;
-- srefloat_test <= srefloat_unscale;
-- simfloat_test <= simfloat_unscale;
end process scaleresult_proc;
</SNIP>

In ModelSim:

VSIM> run
# ** Fatal: (vsim-3421) Value -1.#INF is out of range 1e+308 to
-1e+308.

What gives? Is the scale factor I'm multiplying by somehow causing an
overflow in the floating point? srefloat_unscale and simfloat_unscale
are both reals between -1 and +1 (normalized fixed point), so the
result should be anywhere from -128 to +128 after scaling.

Thanks,
-Brandon

 

[Neo]

initialise the real variables and proceed.

 

[Amit Dua]

uninitialized objects get 'left value of their type.

in this case, the real signals get most -ive value
i.e. -1e+308. When this is multiplied, it overflows.

btw, NCVHDL has an option "-initzero" to initialize
all "integer" and "time" type objects (signals,variables,
generics) in the design to 0 (instead of 'left).
so if this is what you desire, you don't have to
explicitly set for objects of these types.

Thanks.
-Amit.

 

[Brandon]

I tried the above advice, but it did not seem to help.

I think the problem is because the signals are connected to output
ports of the entity that converts my fixed point binary to real:
<SNIP>

architecture behavioral_ar of my_tb is
....
signal srefloat_unscale : real := 0.0;
signal simfloat_unscale : real := 0.0;
signal srefloat_test : real := 0.0;
signal simfloat_test : real := 0.0;
....

begin
sreConvert_ins : entity work.fxdbin2fpdec_g(behavioral_ar)
generic map (dwidth => DWIDTH_C)
port map (fxdbin => sre, fpdec => srefloat_unscale);

simConvert_ins : entity work.fxdbin2fpdec_g(behavioral_ar)
generic map (dwidth => DWIDTH_C)
port map (fxdbin => sim, fpdec => simfloat_unscale);
....
scaleresult_proc: process(srefloat_unscale, simfloat_unscale)
begin
srefloat_test <= srefloat_unscale*2.0**7;
simfloat_test <= simfloat_unscale*2.0**7;
end process scaleresult_proc;

end behavioral_ar;
</SNIP>

Is there anyway around this? I'm also using ModelSim, so ncvhdl
compiler properties are not an option.

 

[Egbert Molenkamp]

Did you also initialize the input in the entity declaration?
e.g.
entity dbbl is
port (x : in real :=0.0 ; y : out real);
end dbbl;

Egbert Molenkamp