A
ALuPin
Hi all,
I have the following piece of VHDL code which
is not accepted in simulation but in synthesis:
constant cCLUSTER : integer := 4;
type cluster_type is array(cCLUSTER-1 downto 0) of std_logic_vector(1
downto 0);
signal ls_addr_cluster : cluster_type;
process(Clk)
begin
if rising_edge(Clk) then
if TxValid='1' then
case Addr is
when "00" => if cCLUSTER >= 1 then
ls_addr_cluster(0) <= Addr;
end if;
when "01" => if cCLUSTER >=2 then
ls_addr_cluster(1) <= Addr;
end if;
when "10" => if cCLUSTER >=3 then
ls_addr_cluster(2) <= Addr;
end if;
when "11" => if cCLUSTER >=4 then
ls_addr_cluster(3) <= Addr;
end if;
end case;
end if;
end if;
end process;
When using cCLUSTER=3 the simulation is aborted with the error
message: "Index value 3 is out of range 2 downto 0".
The if-condition seems not to keep Modelsim from checking
the assignment "ls_addr_cluster(3) <= Addr;" although
cCLUSTER is a constant definition. Synthesis does not complain ...
How can I solve that problem ?
Thank you for your opinion.
Rgds
Andre
I have the following piece of VHDL code which
is not accepted in simulation but in synthesis:
constant cCLUSTER : integer := 4;
type cluster_type is array(cCLUSTER-1 downto 0) of std_logic_vector(1
downto 0);
signal ls_addr_cluster : cluster_type;
process(Clk)
begin
if rising_edge(Clk) then
if TxValid='1' then
case Addr is
when "00" => if cCLUSTER >= 1 then
ls_addr_cluster(0) <= Addr;
end if;
when "01" => if cCLUSTER >=2 then
ls_addr_cluster(1) <= Addr;
end if;
when "10" => if cCLUSTER >=3 then
ls_addr_cluster(2) <= Addr;
end if;
when "11" => if cCLUSTER >=4 then
ls_addr_cluster(3) <= Addr;
end if;
end case;
end if;
end if;
end process;
When using cCLUSTER=3 the simulation is aborted with the error
message: "Index value 3 is out of range 2 downto 0".
The if-condition seems not to keep Modelsim from checking
the assignment "ls_addr_cluster(3) <= Addr;" although
cCLUSTER is a constant definition. Synthesis does not complain ...
How can I solve that problem ?
Thank you for your opinion.
Rgds
Andre