Parameterized precompiled modules

Discussion in 'VHDL' started by Niiranen Miika, Oct 7, 2004.

  1. Hi all!

    I'm wondering whether it is possible to use parameterized precompiled
    modules in VHDL. If I recall correctly, in SystemC it was possible to
    compile parameterized modules "in parallel" when the possible parameters
    were known in advance. Say, a customer knows that he may want to use our
    new adder with bus widths of 8, 16, and 32 bits. Is it possible to
    automate the process of compiling (or even synthesizing) the adder for
    these parameters, i.e., separate bit widths, so that these cases would not
    have to be compiled and labeled separately? Giving the source VHDLs to the
    client is not an option due to IP protection reasons. I use Synopsys
    Design Compiler as a synthesis tool.

    Sorry for this confusing explanation... :)

    Miika Niiranen
     
    Niiranen Miika, Oct 7, 2004
    #1
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  2. Niiranen Miika

    Jim Lewis Guest

    Miika,
    With Synopsys flow, I tend to do this with a wrapper.
    My original rational was so I could have unique design
    names after synthesis without having to rely on the
    synthesis tool to generate the names and such, however,
    it seems this technique would fit well in what you are
    trying to do.

    First I create the generic component. Then I instantiate
    the generic component in a component with the generic
    values specified.

    Generic entity:
    entity Mux2 is
    generic (width : integer ) ;
    port (
    Sel : in std_logic ;
    A : in std_logic_vector(width-1 downto 0) ;
    B : in std_logic_vector(width-1 downto 0) ;
    Y : in std_logic_vector(width-1 downto 0)
    ) ;
    end Mux2 ;

    .....

    Wrapper Entity:
    entity Mux2x8 is
    port (
    Sel : in std_logic ;
    A : in std_logic_vector(7 downto 0) ;
    B : in std_logic_vector(7 downto 0) ;
    Y : in std_logic_vector(7 downto 0)
    ) ;
    end Mux2x8 ;
    architecture WRAPPER of mux2x8 is
    component Mux2 ...

    begin
    u_mux2 : Mux2
    generic map (8)
    port map( Sel, A, B, Y) :

    end WRAPPER ;

    After synthesizing Mux2x8, I remove the hierarchy
    generated by mux2 using the ungroup command.

    Kind of brute force, but seems to simplify the
    synthesis flow and is really the only option for
    you to presynthesize the design and deliver only
    the synthesized code. If you are creating customize
    sizes alot, you should be able to do this with a
    script.


    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



    > Hi all!
    >
    > I'm wondering whether it is possible to use parameterized precompiled
    > modules in VHDL. If I recall correctly, in SystemC it was possible to
    > compile parameterized modules "in parallel" when the possible parameters
    > were known in advance. Say, a customer knows that he may want to use our
    > new adder with bus widths of 8, 16, and 32 bits. Is it possible to
    > automate the process of compiling (or even synthesizing) the adder for
    > these parameters, i.e., separate bit widths, so that these cases would not
    > have to be compiled and labeled separately? Giving the source VHDLs to the
    > client is not an option due to IP protection reasons. I use Synopsys
    > Design Compiler as a synthesis tool.
    >
    > Sorry for this confusing explanation... :)
    >
    > Miika Niiranen
     
    Jim Lewis, Oct 7, 2004
    #2
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