pass an undefined number of datasets

Discussion in 'VHDL' started by Andreas, May 31, 2005.

  1. Andreas

    Andreas Guest

    Hello,
    is there an easy way to pass an undefined number of datasets to an entity?
    My solution is

    entity
    port(count: in integer;
    data : real_vector(0 to 100)
    );
    end entity;

    if one dataset is a real number (could be anything else). 'data' is a
    vector(array), which contains all datasets. its length is 100 if I want
    to pass 100 sets at most. 'count' is the number of datasets really used
    in the current simulation cycle.

    Is there perhabs a more effectiv, better way to pass an undefined number
    of datasets?

    Thanks,

    Andreas
     
    Andreas, May 31, 2005
    #1
    1. Advertising

  2. Andreas

    Neo Guest

    you can use "generic" to define the reqd number of datasets but it has
    to be determined at compile time.
     
    Neo, May 31, 2005
    #2
    1. Advertising

  3. Andreas

    Andreas Guest

    Hi,

    Neo wrote:
    > you can use "generic" to define the reqd number of datasets but it has
    > to be determined at compile time.
    >

    Soory, I've forgotten to say, that the required number has be dynamic
    during simulation and cann't be tetermined at compile time.
     
    Andreas, May 31, 2005
    #3
  4. Andreas

    Neo Guest

    No its not possible. This is hardware description and should be
    determined before it is implemented. You can have the largest possible
    number and then use only a subset of them based on requirement.
     
    Neo, May 31, 2005
    #4
  5. Andreas

    Andreas Guest

    Neo wrote:
    > No its not possible. This is hardware description and should be


    Perhabs VHDL was intended as a hardware description language, but I use
    it primarily as a language for system simulations (in connection with
    the AMS- extension).

    > determined before it is implemented. You can have the largest possible
    > number and then use only a subset of them based on requirement.
    >
     
    Andreas, May 31, 2005
    #5
  6. Andreas wrote:

    > Perhabs VHDL was intended as a hardware description language, but I use
    > it primarily as a language for system simulations


    Then you ought to be using functions
    and procedures instead of entities.

    -- Mike Treseler
     
    Mike Treseler, May 31, 2005
    #6
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. news.microsoft.com
    Replies:
    0
    Views:
    440
    news.microsoft.com
    Apr 12, 2006
  2. Francisco Garcia
    Replies:
    2
    Views:
    471
    Fran Garcia
    Apr 13, 2006
  3. Mantorok Redgormor
    Replies:
    70
    Views:
    1,766
    Dan Pop
    Feb 17, 2004
  4. news.microsoft.com
    Replies:
    0
    Views:
    187
    news.microsoft.com
    Apr 12, 2006
  5. Francisco Garcia
    Replies:
    3
    Views:
    252
    vincent
    Apr 13, 2006
Loading...

Share This Page