Hi all, I've just started learning VHDL so some of my questions may seem
rudimentary...
Is there any way of guaranteeing the state of an output pin on power up?
Is it done from the VHDL or is it a constraint thing or perhaps something
else
Cheers
Alf
Hi Alfonso,
from VHDL point of view, registered outputs can have an asynchronous
reset to get an initial state. Combinatorical signals immediatlely
(that is after their delay) react to their inputs. you may create some
output enable with an and gate or a tristate bufffer to control the
power up behavior.
The other thing is physics. The behavior of the target architecture.
You have to read the datasheet, for CPLD and FPGAs and ask the fab if
you are going to design for ASICs.
The power on behavior depends on the used technology. e.g. most SRAM
based FPGAs hold their I/Os in the tristate while loading their
bitsreams and provide an internal reset signal (and locked signals for
PLLs DCMs etc) to tell the user circuit when to start.
Have a nice synthesis
Eilert