I'm trying to simulate a simple intersection using VHDL for a state machine but I'm getting completely incorrect behavior. All it should do is spend total of 16 cycles in the NS state (8 in NS 8 in NSL) and a total of 8 seconds in the EW state(4 in EW and 4 in EWL) and then repeat itself. It seems to just spend a little time in one place then a long time in another place, without any regard to clock cycles or state assignments. Am I doing something horribly wrong?
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all ;
ENTITY TrafficLight2 IS
PORT(NS,EW,NSL,EWL: IN STD_LOGIC_VECTOR(1 DOWNTO 0);--cars that want to go in those directions
Clk,Reset: IN STD_LOGIC;
GNS,GEW,RNS,REW,GNSL,GEWL: OUT STD_LOGIC);--GNS = greens for North and South, GEW = greens for East and West, GNSL = greens for North and South left lanes, GEWL = greens for East and Weset left lanes
END TrafficLight2;
ARCHITECTURE Behavior OF TrafficLight2 IS
TYPE State_type IS(NSStart,EWStart,GoNS,GoEW,GoNSL,GoEWL);--GoNS=North and South green,GoEW=East and West green,GoNSL=North Left and South Left green,GoEWL=East Left and South Left green
SIGNAL state: State_type;
SIGNAL count: INTEGER RANGE 0 to 16;
BEGIN
PROCESS(Clk)
BEGIN
IF Reset = '1' THEN
state<=NSStart;
ELSIF(Clk'EVENT AND Clk='1') THEN
CASE state IS
WHEN NSStart =>
count <= 16;
state <= GoNS;
WHEN EWStart =>
count <= 8;
state <= GoEW;
WHEN GoNS =>
IF count=8 THEN
state <=GoNSL;
ELSE
count <= count - 1;
END IF;
WHEN GoEW =>
IF count=4 THEN
state <=GoEWL;
ELSE
count <= count - 1;
END IF;
WHEN GoNSL =>
IF count=0 THEN
state<=EWStart;
ELSE
count <= count -1;
END IF;
WHEN GoEWL =>
IF count=0 THEN
state<=NSStart;
ELSE
count <=count-1;
END IF;
END CASE;
END IF;
END PROCESS;
GNS<='1' WHEN state = GoNS ELSE '0';
GEW<='1' WHEN state = GoEW ELSE '0';
RNS<='1' WHEN state = GoEW OR state = GoEWL ELSE '0';
REW<='1' WHEN state = GoNS OR state = GoNSL ELSE '0';
GNSL<='1' WHEN state = GoNSL ELSE '0';
GEWL<='1' WHEN state = GoEWL ELSE '0';
END Behavior;