Problem with register file

[Fi3rizi0]

Hi all,
I try to realize a register file, with register "0" can be only reads
and is full of "0".
When I simulate with multisim, the register 0 is"Undefined" always.
Where I mistake?

thanks


this is the code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity reg_file is

generic (
n_registri : integer :=5; -- Number of register is
2**N_registri
n_bit : integer :=32); -- Register dimension

port (
wen : in std_logic; -- write enable
adx_d : in std_logic_vector(n_registri-1 downto 0); --Register
Address for writing
d : in std_logic_vector(n_bit-1 downto 0); --Data to
writing
clk : in std_logic;
rst_n : in std_logic; --Reset
adx_a : in std_logic_vector(n_registri-1 downto 0); --Register
Address for reading A
a : out std_logic_vector(n_bit-1 downto 0);
adx_b : in std_logic_vector(n_registri-1 downto 0); --Register
Address for reading B
b : out std_logic_vector(n_bit-1 downto 0));

end reg_file;

architecture behavioral of reg_file is

type matrice is array (0 to (2**n_registri)-1) of
std_logic_vector(n_bit-1 downto 0);

constant zero : std_logic_vector(n_bit-1 downto 0) := (others =>
'0');
signal registri : matrice;

begin -- behavioral

-- Register 0 can only be reads;
registri(0) <= conv_std_logic_vector(0,n_bit);

-- purpose: Scrittura D
-- type : sequential
-- inputs : clk, rst_n
-- outputs:
writing: process (clk, rst_n)
begin -- process scrittura
if rst_n = '0' then -- asynchronous reset (active
low)
for i in 1 to (2**n_registri)-1 loop
registri(i) <= (others => '0');
end loop; -- i
elsif clk'event and clk = '1' then -- rising clock edge
if (wen = '1') and (adx_d /=
conv_std_logic_vector(0,n_registri)) then
registri(conv_integer(adx_d)) <= d;
end if;
end if;
end process scrittura;

-- purpose: Lettura porta A
-- type : combinational
-- inputs : adx_a
-- outputs:
lettura_a: process (adx_a,registri)
begin -- process lettura_a

a <= registri(conv_integer(adx_a));

end process lettura_a;

-- purpose: Lettura porta B
-- type : combinational
-- inputs : adx_b
-- outputs:
lettura_b: process (adx_b,registri)
begin -- process lettura_b

b <= registri(conv_integer(adx_b));

end process lettura_b;

end behavioral;