problem with timing simulation

Discussion in 'VHDL' started by JEmoderatz@yahoo.com, Aug 9, 2005.

  1. Guest

    Hi

    I have two problems when simulating a state machine after PAR (place
    and route) using Modelsim6.0 and XST ISE6.3.

    First problem is that I can not find the name of the state in the
    signal list. So it is very hard to trace (debug). Are there any way to
    see the name (or symbol) of the state?

    Second problem is that I have following warning after PAR. It is not
    working in timing simulation.

    WARNING:NetListWriters:303 - Unable to preserve the ordering for port
    bus mux_a on block using the data mux_a<0><1:0>.

    Port ( clk : in std_logic;
    rst : in std_logic;
    ...
    mux_a : out array_mux);

    In package, array_mux is defined

    type array_mux is array (0 to 3) of std_logic_vector(1 downto 0);

    Thankyou for the reply.
     
    , Aug 9, 2005
    #1
    1. Advertising

  2. Guest

    Second problem:

    0 to 3 <--> 1 downto 0

    See?

    Rgds
    André
     
    , Aug 9, 2005
    #2
    1. Advertising

  3. Duane Clark Guest

    wrote:
    > Second problem:
    >
    > 0 to 3 <--> 1 downto 0
    >


    In general that is perfectly acceptable, and I have done it several
    times, though only on internal signals. I have not tried using a two
    dimensional array on pin assignments.

    If the PAR tool allows two dimensional arrays on pins, but did not allow
    the dimensions to be in different directions, then I would consider that
    to be a bug.
     
    Duane Clark, Aug 9, 2005
    #3
  4. Guest

    Hi

    Regarding 2nd problem, I did modification and the same problem occurred
    -:

    array_mux is array (3 downto 0) of std_logic_vector(1 downto 0);

    I suspect that the port with 2 dimensional array type is not supported
    by ISE PAR.
     
    , Aug 10, 2005
    #4
  5. Guest

    Where do you use that array_mux ?

    In signal declaration within the VHDL architecture or as port type
    declaration of the entity?

    Rgds
    André
     
    , Aug 10, 2005
    #5
  6. wrote:


    > Second problem is that I have following warning after PAR. It is not
    > working in timing simulation.
    >
    > WARNING:NetListWriters:303 - Unable to preserve the ordering for port
    > bus mux_a on block using the data mux_a<0><1:0>.
    >
    > Port ( clk : in std_logic;
    > rst : in std_logic;
    > ...
    > mux_a : out array_mux);
    >
    > In package, array_mux is defined
    >
    > type array_mux is array (0 to 3) of std_logic_vector(1 downto 0);


    Just to make shure: You did compile the package before the entity?


    Is this the entity of your topmost component? Then it would be better to
    break the 2D array down to a 1D vector.

    Ralf
     
    Ralf Hildebrandt, Aug 10, 2005
    #6
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. valentin tihomirov
    Replies:
    2
    Views:
    563
    valentin tihomirov
    Jan 5, 2004
  2. mike

    timing simulation problem

    mike, Jul 19, 2005, in forum: VHDL
    Replies:
    2
    Views:
    616
    Andy Peters
    Jul 20, 2005
  3. mike

    timing simulation problem

    mike, Jul 19, 2005, in forum: VHDL
    Replies:
    0
    Views:
    453
  4. Replies:
    1
    Views:
    507
    Hubble
    Aug 22, 2005
  5. jasperng
    Replies:
    0
    Views:
    1,323
    jasperng
    Nov 27, 2008
Loading...

Share This Page