problem with unsigned

Discussion in 'VHDL' started by Apo, Sep 19, 2004.

  1. Apo

    Apo Guest

    Hi All, I have a problem.

    I can't understand why, with my modelsim 5,7c , in some circumstaces I can
    compile the script below but when I'm exporting from EDK project to model
    sim for a behaviourl test of an Ip core it return this error:

    # ** Error:
    C:/ppp/AES_EDK_KVERBAK/pcores/kver_v1_00_a/hdl/vhdl/kver_module.vhd(176):
    identifer unsigned is not visible. Making two objects with the name
    "unsigned" directly visible via use clauses results in a conflict, neither
    object is made directly visible.(LRM Section 10.4).

    Definition include from:

    ieee.std_logic_arith.unsigned

    ieee.numeric_std.unsigned



    The script is:

    TO_UNSIGNED(SBOX(To_INTEGER(unsigned(input(31 downto 24)))), 8)

    it is nested in:

    return word(

    TO_UNSIGNED(SBOX(To_INTEGER(unsigned(input(31 downto 24)))), 8) &

    TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input(23 downto 16)))), 8) &

    TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input(15 downto 8)))), 8) &

    TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input( 7 downto 0)))), 8)

    );

    where Word is

    SUBTYPE word IS std_logic_vector(31 DOWNTO 0);



    Thank you

    Alain
     
    Apo, Sep 19, 2004
    #1
    1. Advertising

  2. Apo wrote:


    > I can't understand why, with my modelsim 5,7c , in some circumstaces I
    > can compile the script below but when I'm exporting from EDK project to
    > model sim for a behaviourl test of an Ip core it return this error:
    >
    > # ** Error:
    > C:/ppp/AES_EDK_KVERBAK/pcores/kver_v1_00_a/hdl/vhdl/kver_module.vhd(176):
    > identifer unsigned is not visible. Making two objects with the name
    > "unsigned" directly visible via use clauses results in a conflict, neither
    > object is made directly visible.(LRM Section 10.4).
    >
    > Definition include from:
    > ieee.std_logic_arith.unsigned
    > ieee.numeric_std.unsigned


    what happens if you do this

    use ieee.numeric_std.all
    -- use ieee.std_logic_arith.unsigned

    ?

    > return word(
    > TO_UNSIGNED(SBOX(To_INTEGER(unsigned(input(31 downto 24)))), 8) &
    > TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input(23 downto 16)))), 8) &
    > TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input(15 downto 8)))), 8) &
    > TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input( 7 downto 0)))), 8)
    > );
    >
    > where Word is
    > SUBTYPE word IS std_logic_vector(31 DOWNTO 0);


    I will assume that you are not really trying to return a subtype.

    -- Mike Treseler
     
    Mike Treseler, Sep 19, 2004
    #2
    1. Advertising

  3. Apo

    Apo Guest

    "Mike Treseler" <> ha scritto nel messaggio
    news:...
    > Apo wrote:
    >
    >
    > > I can't understand why, with my modelsim 5,7c , in some circumstaces I
    > > can compile the script below but when I'm exporting from EDK project to
    > > model sim for a behaviourl test of an Ip core it return this error:
    > >
    > > # ** Error:
    > >

    C:/ppp/AES_EDK_KVERBAK/pcores/kver_v1_00_a/hdl/vhdl/kver_module.vhd(176):
    > > identifer unsigned is not visible. Making two objects with the name
    > > "unsigned" directly visible via use clauses results in a conflict,

    neither
    > > object is made directly visible.(LRM Section 10.4).
    > >
    > > Definition include from:
    > > ieee.std_logic_arith.unsigned
    > > ieee.numeric_std.unsigned

    >
    > what happens if you do this
    >
    > use ieee.numeric_std.all
    > -- use ieee.std_logic_arith.unsigned
    >
    > ?
    >
    > > return word(
    > > TO_UNSIGNED(SBOX(To_INTEGER(unsigned(input(31 downto 24)))), 8) &
    > > TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input(23 downto 16)))), 8) &
    > > TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input(15 downto 8)))), 8) &
    > > TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input( 7 downto 0)))), 8)
    > > );
    > >
    > > where Word is
    > > SUBTYPE word IS std_logic_vector(31 DOWNTO 0);

    >
    > I will assume that you are not really trying to return a subtype.


    What do you mean? how can convert a integer to a std_logic_vector or
    something similar?

    ah.. with your correction it seems work


    > -- Mike Treseler
    >


    Thanks for help

    Alain
     
    Apo, Sep 19, 2004
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Timo Freiberger
    Replies:
    3
    Views:
    974
    Bob Hairgrove
    Oct 30, 2004
  2. George Marsaglia

    Assigning unsigned long to unsigned long long

    George Marsaglia, Jul 8, 2003, in forum: C Programming
    Replies:
    1
    Views:
    706
    Eric Sosman
    Jul 8, 2003
  3. Replies:
    1
    Views:
    463
    Diez B. Roggisch
    Jun 1, 2005
  4. sridhar

    comparing unsigned long and unsigned int

    sridhar, Nov 1, 2004, in forum: C Programming
    Replies:
    6
    Views:
    458
    J. J. Farrell
    Nov 3, 2004
  5. pozz
    Replies:
    12
    Views:
    760
    Tim Rentsch
    Mar 20, 2011
Loading...

Share This Page