problem with vhdl

[burigallego]

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:21:40 12/04/2007
-- Design Name:
-- Module Name: Detector_Flancos - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.Componentes.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
---- library UNISIM;
---- use UNISIM.VComponents.all;
--

entity Detector_Flancos is
port (S_IN,CLK,RESET :in STD_LOGIC;S_OUTut STD_LOGIC);
end Detector_Flancos;

architecture Behavioral of Detector_Flancos is

signal OUT1B,OUT2B: STD_LOGIC;

begin

process (CLK)
begin
If (CLK='1' and CLK'event) then
If RESET='1' then S_OUT<='0';
else
B1:Biestable_D port map(S_IN,CLK,OUT1B);
B2:Biestable_D port map(OUT1B,CLK,OUT2B);
S_OUT<=OUT1B and not(OUT2B);
end if;
end if;
end process;
end Behavioral;

this code generates this error :

parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK

any solution?