Vhdl problem with integers

[djaniel]

Hi,

This might be a pretty basic question but it is giving me a headache!

In my project, I'm receiving a byte through one UART and I want to receive & store 32 bytes in one signal declared as

--Buffer for data storage
signal data_received : STD_LOGIC_VECTOR (255 downto 0);

To know where to store bytes in "data_received" I use one integer declared as follows

p_receive: process (clk)	
	--Integer for vector manipulation
	variable contador: integer :=255;
begin

So, when I receive one byte I use this line. I store the byte received in the first 8 bits of "data_received".

data_received(contador downto contador-7) <= rx_data;

Contador is the variable I use to know when I have received 32 bytes, I do that with an if looking like this:

--State change
	if(contador > 7 )then
		control_sm	<= ACKNOWLEDGE;
		contador 	:= contador-8;
	else 
		control_sm 	<= DONE;
	end if;

Notice I decrement contador each time. It works fine when receiving

After receiving 32 bytes I intend to send them back to my pc. I reset contador with:

contador	:= 255;

and use the same technic for setting the data to be sent:

tx_data	<= data_received(contador downto contador-7);
tx_req	<= '1';

The THING is, after sending the first byte this if doesn't work:

if(contador > 7 )then
	control_sm	<= SEND;
	contador 	:= contador-8;
else							
	control_sm <= IDLE;
end if;

As if I haven't reset contador to 255
And then, after sending the first byte it goes to IDLE state. Just because the 'if' condition is false, but I'm sure I reset it to 255!

I added this if just before the last one I mentioned, counter is a variable wired to led's on my board and I get the "101010".

if contador = 255 then
	counter <= "111111";
else
	counter <= "101010";
end if;

Can you give a hand with this?

Thanks
@djaniel

Here's the code

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:43:33 12/29/2010 
-- Design Name: 
-- Module Name:    Control_Rx - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Control_Rx is
    Port (	-- control
				clk			: in  STD_LOGIC;
				reset			: in  STD_LOGIC;
				
				--Rx 
				rx_ready 	: in  STD_LOGIC;
				rx_data	 	: in  STD_LOGIC_VECTOR (7 downto 0);
				rx_flag		: out STD_LOGIC;
				
				--Tx
				tx_data		: out STD_LOGIC_VECTOR (7 downto 0);
				tx_req		: out STD_LOGIC;
				tx_end		: in  STD_LOGIC;
								
				counter   : inout STD_LOGIC_VECTOR (5 downto 0);
				
				--Cypher control
				StartStop	: out STD_LOGIC;
				StringKey	: inout STD_LOGIC_VECTOR (255 downto 0)
			);
end Control_Rx;

architecture Behavioral of Control_Rx is
-------------------- SIGNALS -------------------------
--State Machine
type state is ( IDLE, ACKNOWLEDGE, DONE, WORK, SEND, TEND );
signal control_sm :state :=IDLE;
--Buffer for data storage
signal data_received : STD_LOGIC_VECTOR (255 downto 0);
begin	
	p_receive: process (clk)	
	--Integer for vector manipulation
	variable contador: integer :=255;
	begin
		if (clk'event and clk ='1') then
			--State machine
			case control_sm is
				--idle state
				when IDLE =>
					--default value
					tx_req <= '0';
					--Data arrival
					if rx_ready = '1' then
						counter <= counter + 1;
						rx_flag <= '1';
						--data storage						
						data_received(contador downto contador-7) <= rx_data;						
						--State change
						if(contador > 7 )then
							control_sm	<= ACKNOWLEDGE;
							contador 	:= contador-8;
						else 
							control_sm 	<= DONE;
						end if;
					end if;
				--byte acknowledged
				when ACKNOWLEDGE =>
					if rx_ready = '0' then
						control_sm <= IDLE;
						rx_flag <= '0';
					end if;
				--Data received
				when DONE =>
					--Start cypher
					StartStop <= '0';
					--Reset variables					
					counter	<= "000000";
					control_sm <= WORK;
				--Cypher working
				when WORK =>
					control_sm <= SEND;
					contador	:= 255;
				--Send Data
				when SEND =>
					--send data stored
					tx_data	<= data_received(contador downto contador-7);
					tx_req	<= '1';
					control_sm <= TEND;
				-- Wait for transmition to end
				when TEND =>
					if tx_end = '1' then
						tx_req <= '0';
						if contador = 255 then
							counter <= "111111";
						else
							counter <= "101010";
						end if;
						--State change
						if(contador > 7 )then
							control_sm	<= SEND;
							contador 	:= contador-8;
						else							
							control_sm 	<= IDLE;
						end if;
					end if;
				when others =>
					control_sm	<= IDLE;
			end case;
			--reset state
			if reset ='1'  then
				StringKey	<=	(others=>'0');
				control_sm	<= IDLE;
				tx_req 		<= '0';
				StartStop	<=	'1';
				contador		:= 255;
				counter		<= "000000";
			end if;
		end if;
	end process;
end Behavioral;

 

[Philippe.Faes]

Hi Djaniel,

Taking a short look, I can't spot your problem. But from you talking about LEDs, I presume you are debugging in hardware. Wouldn't it be easier if you run a simulation first? It should be easy enough to write a testbench for this single module, right? Good luck and keep us posted!