Procedure for creating a signal from file

Discussion in 'VHDL' started by solosys, Aug 1, 2007.

  1. solosys

    solosys

    Joined:
    Jul 17, 2007
    Messages:
    2
    Does anyone know of a procedure that will read binary data from a file, and instead of writing the data to a ram/rom, it will create a signal of std_logic_vector
    solosys, Aug 1, 2007
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Michael Pronath
    Replies:
    1
    Views:
    1,141
    Diez B. Roggisch
    Jan 3, 2005
  2. Jack Orenstein

    threading.Thread vs. signal.signal

    Jack Orenstein, Sep 18, 2005, in forum: Python
    Replies:
    0
    Views:
    452
    Jack Orenstein
    Sep 18, 2005
  3. Weng Tianxiang
    Replies:
    2
    Views:
    637
    Jonathan Bromley
    Jan 30, 2007
  4. Nicolas Moreau
    Replies:
    9
    Views:
    3,086
  5. dibacco73
    Replies:
    1
    Views:
    630
    joris
    Feb 12, 2009
Loading...

Share This Page