Procedures in testbench confusion

Discussion in 'VHDL' started by Peter Hermansson, Aug 25, 2004.

  1. Hi,

    I am rather confused about the use of procedures in testbenches. My
    intention is to model an I2C-bus with pullup resistors. My testbench
    consists of a testprocess with a couple of procedures;reset, do
    something, check that, do something else, check that etc.
    If I set the I2C SCL and SDA line to 'H' in the reset-procedure and
    then to '0' in another later procedure, everything is fine. But if set
    them to 'H' outside the test-process, in the parallell part of the
    code, both are 'U' from the very beginning of the simulation.
    Both SCL and SDA are declared std_logic so why isnt the conflict
    between 'H' and '0' resolved? And why are they 'U' from the beginning,
    not just from the point in time were they are set to '0'?

    I am sure that there is a very basic answer to this question and I
    would be grateful if someone could provide it.

    Regards, Peter
    Peter Hermansson, Aug 25, 2004
    #1
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  2. On 25 Aug 2004 00:34:59 -0700, (Peter
    Hermansson) wrote:

    >Hi,
    >
    >I am rather confused about the use of procedures in testbenches. My
    >intention is to model an I2C-bus with pullup resistors. My testbench
    >consists of a testprocess with a couple of procedures;reset, do
    >something, check that, do something else, check that etc.
    >If I set the I2C SCL and SDA line to 'H' in the reset-procedure and
    >then to '0' in another later procedure, everything is fine. But if set
    >them to 'H' outside the test-process, in the parallell part of the
    >code, both are 'U' from the very beginning of the simulation.
    >Both SCL and SDA are declared std_logic so why isnt the conflict
    >between 'H' and '0' resolved? And why are they 'U' from the beginning,
    >not just from the point in time were they are set to '0'?


    Every process in VHDL represents a driver on each signal assigned
    within that process. Continuous assignments, like your external
    pullup assignments, are processes too. So, at time 0 you have
    your pullup process assigning 'H', and your test process assigning
    the initial value of the signal, which is 'U'. Since 'U' is the
    strongest of all std_logic values, you see 'U' until the test
    process assigns a different value.

    Since it's a test bench, one possible solution is to give the I2C
    signals initial values:

    signal SCL, SDA: std_logic := 'H'; -- or 'Z' if you have a pullup

    This means that the initial value of SCL and SDA *in every process
    that drives them* is 'H'.

    I don't really see why the external pullup process is useful. Your
    test process must drive the signal to '0' when it wants zero, and
    then to either 'H' or 'Z' when it wants the pullup to drive 1.
    Consequently, you save yourself nothing by adding the external
    pullup process.

    HTH
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Aug 25, 2004
    #2
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  3. Jonathan Bromley <> wrote in message news:<>...
    >
    > I don't really see why the external pullup process is useful. Your
    > test process must drive the signal to '0' when it wants zero, and
    > then to either 'H' or 'Z' when it wants the pullup to drive 1.
    > Consequently, you save yourself nothing by adding the external
    > pullup process.
    >
    > HTH
    > --
    > Jonathan Bromley, Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
    >
    > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    > Tel: +44 (0)1425 471223 mail:
    > Fax: +44 (0)1425 471573 Web: http://www.doulos.com
    >
    > The contents of this message may contain personal views which
    > are not the views of Doulos Ltd., unless specifically stated.



    Thanks!

    /Peter
    Peter Hermansson, Aug 25, 2004
    #3
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