Process or concurrent statement?

[Daniel]

Hello,
I'm newer in VHDL and always had this question:
which practice is best from these two:

a)
clk1 <= '1' when (counter32b = PERIOD_1) else '0',
clk2 <= '1' when (counter32b = PERIOD_2) else '0',
clk3 <= '1' when (counter32b = PERIOD_3) else '0',


b)

process(clk)
begin

 

[Daniel]

Hello,
I'm newer in VHDL and always had this question:
which practice is best from these two:

a)
clk1 <= '1' when (counter32b = PERIOD_1) else '0',
clk2 <= '1' when (counter32b = PERIOD_2) else '0',
clk3 <= '1' when (counter32b = PERIOD_3) else '0',

b)

process(clk)
begin

The question was not complete but I thing you can figure what's next.
Anyway, hara is the rest:


b)
process(clk)
begin
clk1 <= '0';
clk2 <= '0';
clk3 <= '0';
if rising_edge(clk)
case counter32b of
when PERIOD_1 => clk1 <= '1';
when PERIOD_2 => clk1 <= '1';
when PERIOD_3 => clk1 <= '1';
when others => NULL;
end if;
end process,

 

[Symon]

Hi Daniel,
'a' and 'b' are not equivalent. It's like asking if apples are better than
asphalt. FWIW, 'a' will synthesise to combinational logic, 'b' to
combinational logic and some flip flops clocked by 'clk'.
HTH.,Syms.

 

[Daniel]

Hi Daniel,
'a' and 'b' are not equivalent. It's like asking if apples are better than
asphalt. FWIW, 'a' will synthesise to combinational logic, 'b' to
combinational logic and some flip flops clocked by 'clk'.
HTH.,Syms.

Hi,
I use these clocks to trigger three events. The option without flip-
flip will result in a simpler async logic.
With 'clk' running at 100Mhz, the flip-flip option would be beter.
Thanks for your help.
Daniel.

 

[KJ]

Hi,
I use these clocks to trigger three events. The option without flip-
flip will result in a simpler async logic.

Simpler than what?

With 'clk' running at 100Mhz, the flip-flip option would be beter.

Better than what?

If your intention is to then use the signals 'clk1', 'clk2' and 'clk3'
as the clock inputs to some other processes (as you alluded to by
saying "I use these clocks to trigger three events") then here are
some tips if you plan to implement the design in an FPGA.

1. Don't do that.
2. Really...don't do that...both approaches are bad.
3. The combinatorial approach is worse...
4. The synced up version is nearly just as bad.
5. Are you getting the point? Don't do it that way.

Anyway, the way you 'should' use the various clk1...clk3 signals in
your design would be

process(clk)
begin
if rising_edge(clk) then
if (clk1 = '1') then
-- Do whatever you were thinking of doing on rising_edge(clk1)
here
end if;
end if;
end process;

Repeat this template for 'clk2' and 'clk3'.

If you insist on trying to use 'clk1', 'clk2' and 'clk3' to clock
other things then I wish you good luck with your timing analysis and
even more good luck with getting the design to be stable over
temperature ranges. Creating gated clocks in FPGAs is not good
practice because inevitably the multiple clock domains need to
communicate with each other and there is always going to be some
uncontrollable skew between 'clk', 'clk1', 'clk2' and 'clk3' that
simply doesn't exist if you use a synchronous design approach (i.e.
using only 'clk' to clock anything).

Kevin Jennings

 

[Daniel]

Hi,
ok, I get the point. I'll follow your advice... by the way, can I ask
you for a good reference where I can read about best aproches to
digital design in FPGA. I've been searching in the internet but I'm
overhelmed by such a lot information.
Thanks,
Daniel.

 

[Thomas Stanka]

process(clk)
begin
clk1 <= '0';
clk2 <= '0';
clk3 <= '0';
if rising_edge(clk)
case counter32b of
when PERIOD_1 => clk1 <= '1';
when PERIOD_2 => clk1 <= '1';
when PERIOD_3 => clk1 <= '1';
when others => NULL;
end if;
end process,

I just wonder what your synthesis tools creates out of this process. A
good tool will complain as you mix combinatorial and sequential
template in one process. But I guess you made some copy&paste errors,
as the code above contains several syntax errors and at least two c&p
errors.

if you'd wrote
if rising_edge(clk) then
clk1 <= '0';
case counter32
when PERIOD1 => clk1 <= '1'
......
end case

You would have a correct sequential template, but as Symon stated this
is something different than the combinatorial statement from a) which
should be easy observable in a simulation.

bye Thomas