Process Statements in VHDL

[samsky electronique]

Hi I have a question

Here is an example

process(sig1,sig2,A,B,C)
begin
if (A > "001" and B > "010") then
sig1 <= '1';
else
sig1 <= '0';
end if;

if (C > "011" and sig1 = '0') then
sig2 <= '1';
else
sig2 <= '0';
end if;

end process;

It this advisable to write code like this, or should sig1 be in a
different process. What generally happens when a signal is assigned to
and also read to in the same process. What would happen if i have the
sig1 if-then-else statement, below the sig2 if-then-else statement, how
would the simulator behave ?

appreciate all the detail that I can get.

 

[Ralf Hildebrandt]

process(sig1,sig2,A,B,C)
begin
if (A > "001" and B > "010") then
sig1 <= '1';
else
sig1 <= '0';
end if;

if (C > "011" and sig1 = '0') then
sig2 <= '1';
else
sig2 <= '0';
end if;

end process;

It this advisable to write code like this, or should sig1 be in a
different process.

I would suggest to use a 2nd process for sig2, because to avoid
unnessecary computation for the simulator.

If signal A changes, the simulator has to evaluate the if-condition for
sig2 too, but this is a waste of computation.

The test for sig1 = '0' tests always the /old/ value of sig1. If sig1
has changed, sig2 will not be updated in the same simulator step. But
this does not lead to problems, because the sensitivity list is complete
and therefore the process is trigered again after sig1 has changed und
then the if-condition for sig2 ist evaluated using the new correct value
for sig1.

-> It is not wrong to code it so, but may be misleading if you read the
code later and leads to unnessecary computation of the simulator.


Ralf

 

[aaaaaa]

Hi,
Yes, u can assign the two signals in a process but the difference will be
like as---
value of sig1 will be updated when the process is ended and so the last
sig1 value will be checked on the same process.
rgds
Anupam Garg