Quartus II LPM simulation

Discussion in 'VHDL' started by feiman, Feb 12, 2009.

  1. feiman

    feiman

    Joined:
    Oct 11, 2008
    Messages:
    1
    Hi everyone,
    I'm newie in HDL languages.
    I wanted to simulate in Altera Quartus II RAM based Shifter from built-in models - LPM.
    When I simulate independent model from LPM library everything is fine / no warrning, no errors.
    But when I simulate this model as a part of another block, simulation doesn't work - it gives warrning like posted below - it ignores som outlets and I don't now why, because in hardware implementation it works allright. So that's my bloblem.

    I will introduce cocrete example:

    This is the whole source code I simulate

    module RAW2RGB( oRed,
    oGreen,
    oBlue,
    oDVAL,
    iX_Cont,
    iY_Cont,
    iDATA,
    iDVAL,
    iCLK,
    iRST );

    input iX_Cont;
    input iY_Cont;
    input [9:0] iDATA;
    input iDVAL;
    input iCLK;
    input iRST;
    output [9:0] oRed;
    output [9:0] oGreen;
    output [9:0] oBlue;
    output oDVAL;
    wire [9:0] mDATA_0;
    wire [9:0] mDATA_1;
    reg [9:0] mDATAd_0;
    reg [9:0] mDATAd_1;
    reg [9:0] mCCD_R;
    reg [10:0] mCCD_G;
    reg [9:0] mCCD_B;
    reg mDVAL;

    assign oRed = mCCD_R[9:0];
    assign oGreen = mCCD_G[10:1];
    assign oBlue = mCCD_B[9:0];
    assign oDVAL = mDVAL;

    Line_Buffer u0 ( .clken(iDVAL),
    .clock(iCLK),
    .shiftin(iDATA),
    .taps0x(mDATA_1),
    .taps1x(mDATA_0) );

    always@(posedge iCLK or negedge iRST)
    begin
    if(!iRST)
    begin
    mCCD_R <= 0;
    mCCD_G <= 0;
    mCCD_B <= 0;
    mDATAd_0<= 0;
    mDATAd_1<= 0;
    mDVAL <= 0;
    end
    else
    begin
    mDATAd_0 <= mDATA_0;
    mDATAd_1 <= mDATA_1;
    mDVAL <= {iY_Cont|iX_Cont} ? 1'b0 : iDVAL;
    if({iY_Cont,iX_Cont}==2'b01)
    begin
    mCCD_R <= mDATA_0;
    mCCD_G <= mDATAd_0+mDATA_1;
    mCCD_B <= mDATAd_1;
    end
    else if({iY_Cont,iX_Cont}==2'b00)
    begin
    mCCD_R <= mDATAd_0;
    mCCD_G <= mDATA_0+mDATAd_1;
    mCCD_B <= mDATA_1;
    end
    else if({iY_Cont,iX_Cont}==2'b11)
    begin
    mCCD_R <= mDATA_1;
    mCCD_G <= mDATA_0+mDATAd_1;
    mCCD_B <= mDATAd_0;
    end
    else if({iY_Cont,iX_Cont}==2'b10)
    begin
    mCCD_R <= mDATAd_1;
    mCCD_G <= mDATAd_0+mDATA_1;
    mCCD_B <= mDATA_0;
    end
    end
    end

    endmodule

    module Line_Buffer (
    clken,
    clock,
    shiftin,
    shiftout,
    taps0x,
    taps1x);

    input clken;
    input clock;
    input [9:0] shiftin;
    output [9:0] shiftout;
    output [9:0] taps0x;
    output [9:0] taps1x;

    wire [19:0] sub_wire0;
    wire [9:0] sub_wire3;
    wire [19:10] sub_wire1 = sub_wire0[19:10];
    wire [9:0] sub_wire2 = sub_wire0[9:0];
    wire [9:0] taps1x = sub_wire1[19:10];
    wire [9:0] taps0x = sub_wire2[9:0];
    wire [9:0] shiftout = sub_wire3[9:0];

    altshift_taps altshift_taps_component (
    .clken (clken),
    .clock (clock),
    .shiftin (shiftin),
    .taps (sub_wire0),
    .shiftout (sub_wire3));
    defparam
    altshift_taps_component.lpm_type = "altshift_taps",
    altshift_taps_component.number_of_taps = 2,
    altshift_taps_component.tap_distance = 3,
    altshift_taps_component.width = 10;


    endmodule

    ...and here are warrnings which are outputed after simulation


    Warning: Ignored node in vector source file. Can't find corresponding node name "mCCD_G[0]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_0[9]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_0[8]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_0[7]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_0[6]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_0[5]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_0[4]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_0[3]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_0[2]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_0[1]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_0[0]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_1[9]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_1[8]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_1[7]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_1[6]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_1[5]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_1[4]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_1[3]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_1[2]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_1[1]" in design.
    Warning: Ignored node in vector source file. Can't find corresponding node name "mDATA_1[0]" in design.
    Warning: Can't find node "Line_Buffer:u0|taps0x[9]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps0x[8]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps0x[7]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps0x[6]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps0x[5]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps0x[4]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps0x[3]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps0x[2]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps0x[1]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps0x[0]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps1x[9]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps1x[8]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps1x[7]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps1x[6]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps1x[5]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps1x[4]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps1x[3]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps1x[2]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps1x[1]" for functional simulation. Ignored vector source file node.
    Warning: Can't find node "Line_Buffer:u0|taps1x[0]" for functional simulation. Ignored vector source file node.

    Could someone help me where is the problem why simulator ignore outlets tapsx? I can't resolve this problem for a long time.

    Thank you very much for answers!
    feiman, Feb 12, 2009
    #1
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