Question about signals

Discussion in 'VHDL' started by Ardni, Oct 31, 2008.

  1. Ardni

    Ardni

    Joined:
    Jul 8, 2008
    Messages:
    23
    Hi,
    I have a basic question that I can´t get my head around.

    In the following process I have 1 signal which is mapped to an output and 4 inputs.


    process(clk)
    begin
    if rising_edge (clk)
    ouput_signal <= input_signal_1 AND (NOT input_signal_2);
    input_signal_1 <= input_signal_3 OR (NOT input_signal4);
    end if;
    end process;


    My question is, When the clk edge arrives, does the process takes the values of each of the signals at that moment in time and do the calculations. In which case the changing of input_signal_1 would not affect the state of output_signal. (Is it tue to say that output_signal already has the result of the logic statement and that it will be latched on the clock edge?)

    OR

    If for example input_signal_3 had changed since the last clock edge and lets say input_signal_1 then changed 3 ns later...could the changing of input_signal_1 have a negative effect when output_signal is being assigned. i.e. input_signal 1 could be in the process of changing, or could have already changed or may not have changed yet.

    Maybe the process above is bad design practise? But I just want to have a better understanding of what would actually happen.

    I hope I have explained it clearly enough. If not please let me know.

    Thanks
    Ardni, Oct 31, 2008
    #1
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  2. Ardni

    jeppe

    Joined:
    Mar 10, 2008
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    Location:
    Denmark
    Rising_edge and signals gives F/F's

    Hi

    A quick answer
    When ever you gives a signal a value inside a "if rising_edge(clk) then"
    will you get a F/F.
    The result of your circuit can be seen below - the XOR just a minor adjustment.

    Use a variable for input_signal_1 if you would avoid the leftmost F/F
    [​IMG]
    The source code
    [​IMG]
    The blue line = Input_signal_1
    [​IMG]



    Your welcome
    Jeppe
    jeppe, Oct 31, 2008
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  3. Ardni

    jeppe

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    Extra information - If you use variables can you "avoid" internale F/F's but beware of the order of statements

    [​IMG]

    [​IMG]
    jeppe, Oct 31, 2008
    #3
  4. Ardni

    Ardni

    Joined:
    Jul 8, 2008
    Messages:
    23
    Thanks for the replies Jeppe,
    I understand what you say about the variables. It something I hadn't taken into account earlier.

    But if I don't use a variable I am not clear on what will happen. Is the result dependent on propagation delays? Is the synthezised circuit unsafe/unstable?

    Also is it rue that a signal should not appear on the left hand side and right hand side of different statements inside the same process? (I thin k I read something along those lines at one stage)

    Thank you again so much for your help.
    Ardni, Nov 4, 2008
    #4
  5. Ardni

    jeppe

    Joined:
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    Messages:
    348
    Location:
    Denmark
    Well all circuts depends at propergation delays and hence must you choose the max clock frequency in order to avoid problems.

    No - your circuit not unsafe or unstable. In fact will you be able to use a higher frequency this way.

    But as you can watch at the first figure will there be used two F/F's instead of one. If you move the "input_signal_1 <= ..... " outside the process will you only ask for a single F/F.

    No you migth use signals at both right and left side - specially if we are talking about clock-driven processes.

    Hope this useful
    Jeppe
    jeppe, Nov 5, 2008
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