question on record types

Discussion in 'VHDL' started by FPGA, Jan 30, 2008.

1. FPGAGuest

I have defined two functions as below

function complexMult (a_i,a_q,b_i,b_q: signed) return complex is
variable a,b : complex;
variable result : complex;
begin
assert a_i = a_q report "Error : complexMult - a_i and a_q are not
of equal length."
severity error;

assert b_i = b_q report "Error : complexMult - a_i and a_q are not
of equal length."
severity error;

a.i := a_i;
a.q := a_q;
a.max := a_i'length;
b.i := b_i;
b.q := b_q;
b.max := b_i'length;
result := complexMult(a,b);
return result;
end function complexMult;

function complexMult (a,b: complex) return complex is
variable result : complex;
begin
result.max := maxVal(a.max,b.max) + 1;
result.i := ((a.i * b.i) - (a.q * b.q));
result.q := ((a.i * b.q) + (b.i * a.q));
return result;
end function complexMult;

I am not sure if i can use the same record type for result and inputs
a and b. Note that a and b can be of different lengths. Output
"result" is going to be max(a'length, b'length) + 1 .. I add a one for
the overflow and underflow that can be generated from the addition and
subtraction.

In the simulation , for eg : if a'length = 10 and b'length =5 then I
want result'length = 11. I am trying to do this by not declaring
different record types for input and outputs. Can i do this? If so,
should the testbench be described as follows

a.max <= 10;
a.i <= ".. 10 bits ...";
a.q <= " .. 10 nits...";
b.max <= 10;
b.i <= ".. 5 bits ...";
b.q <= " .. 5 bits...";