Range constants?

Discussion in 'VHDL' started by Tim Hubberstey, Jun 25, 2004.

  1. It is often necessary to extract portions of a vector using a slice.
    Whenever I do this, I use constants for maintainability. I have been
    using what I refer to as "range constants" where I define a vector
    constant that I don't intend to use directly and then use the 'range
    attribute on it to define a slice:

    --------
    -- define a "range constant" in a package
    constant SomeField : std_logic_vector(21 downto 15)
    := (others => 'X');
    --------
    out_vec <= source_vec(SomeField'range);
    --------

    While this works quite well, it seems somewhat messy. Is there a cleaner
    way to do this?
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
     
    Tim Hubberstey, Jun 25, 2004
    #1
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  2. Tim Hubberstey wrote:

    > constant SomeField : std_logic_vector(21 downto 15)
    > := (others => 'X');
    > out_vec <= source_vec(SomeField'range);
    > While this works quite well, it seems somewhat messy. Is there a cleaner
    > way to do this?


    That does the job.
    I might declare and use
    an array or record type to do the same thing.

    -- Mike Treseler
     
    Mike Treseler, Jun 26, 2004
    #2
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  3. On Fri, 25 Jun 2004 18:44:58 GMT, Tim Hubberstey <>
    wrote:

    [...]

    >-- define a "range constant" in a package
    > constant SomeField : std_logic_vector(21 downto 15)
    > := (others => 'X');
    >--------
    > out_vec <= source_vec(SomeField'range);
    >--------
    >
    >While this works quite well, it seems somewhat messy. Is there a cleaner
    >way to do this?


    Subtypes?

    subtype SomeFieldRange is natural range 21 downto 15;
    -----------
    out_vec <= source_vec(SomeFieldRange);

    Make sure your subtype has the same direction (to/downto)
    as the subscripts of source_vec.

    Cheers
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Jun 29, 2004
    #3
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