Real port types in VHDL

Discussion in 'VHDL' started by yaseenzaidi@netzero.com, Aug 14, 2008.

  1. Guest

    Hello all,

    Which VHDL simulator with waveform analyzer supports real type ports?
    Both ModelSim and NCSIM allow real type computations but are shy of
    the real type ports.

    Yaseen
    , Aug 14, 2008
    #1
    1. Advertising

  2. Alan Fitch wrote:

    > Here's my code which works,


    It does, but why the break with local traditions? ;)

    I inserted a few of these: report (real'image(o));
    and I can see it in text:

    # vsim -c etb
    # Loading work.etb(bench)
    # Loading work.real_port(synth)
    VSIM 1> run
    # ** Note: -1.000000e+308
    # Time: 0 ns Iteration: 0 Instance: /etb
    # ** Note: 0.000000e+00
    # Time: 10 ns Iteration: 0 Instance: /etb
    # ** Note: 2.420000e+00
    # Time: 20 ns Iteration: 0 Instance: /etb
    VSIM 2>

    Thanks for the posting.

    -- Mike Treseler
    Mike Treseler, Aug 14, 2008
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. senthil
    Replies:
    5
    Views:
    1,376
    senthil
    Jan 24, 2004
  2. Replies:
    2
    Views:
    8,651
    Jim Lewis
    Mar 21, 2006
  3. Candida Ferreira

    Arrays of real in the port declaration

    Candida Ferreira, Mar 25, 2006, in forum: VHDL
    Replies:
    3
    Views:
    1,426
    Candida Ferreira
    Mar 26, 2006
  4. Curious Trigger
    Replies:
    2
    Views:
    1,810
    Curious Trigger
    Sep 9, 2006
  5. afd
    Replies:
    1
    Views:
    8,301
    Colin Paul Gloster
    Mar 23, 2007
Loading...

Share This Page