Record Creation in VHDL

[Smi]

HI

I have created one record to make a frame fromat as follows
type packet record is
{
preambler:std_logic_vector(3 downto 0);
sync_bit:std_logic_vector(3 downto 0);
data:std_logic;
}
signal tx_packet,rx_packetacket
my frame should be in format preambler,sync_bit,data.. now i need to
send all this tx_packet to hardware to any gpio pin serially can any
body tel me that how to do coding for this
please help me out

 

[KJ]

HI

I have created one record to make a frame fromat as follows
type packet record is
{
  preambler:std_logic_vector(3 downto 0);
sync_bit:std_logic_vector(3 downto 0);
data:std_logic;}

signal tx_packet,rx_packetacket
my frame should be in format preambler,sync_bit,data.. now i need to
send all this tx_packet to hardware to any gpio pin serially can any
body tel me that how to do coding for this
please help me out

There's two steps to this. First create a std_logic_vector out of
your record. Peruse my post in this group called 'Length of range'
for more info and links to details on how I would do that step.

http://groups.google.com/group/comp...46114/05b06bca6030ed95?hl=en#05b06bca6030ed95

Next you need a parallel to serial conversion. The input to this is
the vector created above. The output is your serial stream. Parallel
to serial conversion can be nothing more than a shift register and a
counter to know when you're done.

These two steps can be combined into one which essentially creates a
converter from your record into a serial data stream. Doing so though
is probably less useful than creating the individual parts since the
technique of step #1 can be applied to many other cases, the serial to
parallel convertor can be reused as-is. The combined covertor though
will probably never be used again.

Kevin Jennings