Recursive structures and Quartus?

Discussion in 'VHDL' started by dgreig, Dec 7, 2009.

  1. dgreig

    dgreig Guest

    Hi List

    I have run into a problem with Quartus synthesis, namely recursive
    intantiation. Don't have the sane issue with Synopsis, AldecHDL or
    Modelsim. Here is a simple example fanout tree (Ashenden - going back
    to basics to figure the issue), but first the Quartus 9.1 message:

    Error (10504): VHDL error at fanout_tree.vhd(58): slice that is
    assigned to target slice has 4 elements, but must have same number of
    elements as target slice (2)

    library IEEE;
    use IEEE.std_logic_1164.all;
    --
    ============================================================================--
    entity fanout_tree is
    generic(
    height : natural
    );
    port(
    fan_i : in std_logic;
    fan_o : out std_logic_vector(0 to (2**height) - 1)
    );
    end entity fanout_tree;
    --
    ============================================================================--

    --
    ============================================================================--
    architecture recursive of fanout_tree is
    --------------------------------------------------------------------------------
    --------------------------------------------------------------------------------
    begin
    --------------------------------------------------------------------------------
    g_tree_buff : if (height = 0) generate
    fan_o(0) <= fan_i;
    end generate g_tree_buff;


    g_tree : if (height > 0) generate
    signal buff_0_s : std_logic;
    signal buff_1_s : std_logic;
    begin
    buff0 : entity work.buff(rtl)
    port map(
    buff_i => fan_i,
    buff_o => buff_0_s
    );

    subtree0 : entity work.fanout_tree(recursive)
    generic map(
    height => (height - 1)
    )
    port map(
    fan_i => buff_0_s,
    fan_o => fan_o(0 to (2**(height - 1)) - 1)
    );
    ----------------------------------------
    buff1 : entity work.buff(rtl)
    port map(
    buff_i => fan_i,
    buff_o => buff_1_s
    );

    subtree1 : entity work.fanout_tree(recursive)
    generic map(
    height => (height - 1)
    )
    port map(
    fan_i => buff_1_s,
    fan_o => fan_o( (2**(height - 1)) to (2**height) - 1)
    );
    end generate g_tree;
    --
    ============================================================================--
    end architecture recursive;

    Can anyone confirm if Quartus is capable of recursive instantiation
    with '93 settings? I'ts going to be a DSP nightmare if not!!

    Best Regards
    dgreig, Dec 7, 2009
    #1
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  2. dgreig

    Andy Guest

    On Dec 7, 5:46 pm, Alan Fitch <> wrote:
    > dgreig wrote:
    > > Hi List

    >
    > > I have run into a problem with Quartus synthesis, namely recursive
    > > intantiation. Don't have the sane issue with Synopsis, AldecHDL or
    > > Modelsim. Here is a simple example fanout tree (Ashenden - going back
    > > to basics to figure the issue), but first the Quartus 9.1 message:

    >
    > > Error (10504): VHDL error at fanout_tree.vhd(58): slice that is
    > > assigned to target slice has 4 elements, but must have same number of
    > > elements as target slice (2)

    >
    > >                    subtree1 : entity work.fanout_tree(recursive)
    > >                            generic map(
    > >                                    height  => (height - 1)
    > >                            )
    > >                            port map(
    > >                                    fan_i   => buff_1_s,
    > >                                    fan_o   => fan_o( (2**(height - 1)) to (2**height) - 1)
    > >                            );

    >
    > <snip>
    >
    > > Can anyone confirm if Quartus is capable of recursive instantiation
    > > with '93 settings? I'ts going to be a DSP nightmare if not!!

    >
    > > Best Regards

    >
    > I've tried recursive instantation in Quartus, and it worked fine.
    > However I don't think you can use direct instantiation - you must use
    > component declarations (otherwise how can you instance the component
    > within itself?)
    >
    > regards
    > Alan
    >
    > --
    > Alan Fitch- Hide quoted text -
    >
    > - Show quoted text -


    Since you only have one architecture (recursive), you do not need to
    specify the architecture in the direct entity instantiation, just
    work.fanout_tree.

    IINM, that way you still don't have to use components/configurations.
    As long as the entity itself is compiled before the entity (which is
    required anyway), it should work fine. When you specify the
    architecture in the entity instantiation, it too must already be
    compiled.

    Andy
    Andy, Dec 8, 2009
    #2
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  3. dgreig

    Andy Guest

    On Dec 8, 9:45 am, Andy <> wrote:
    > On Dec 7, 5:46 pm, Alan Fitch <> wrote:
    >
    >
    >
    >
    >
    > > dgreig wrote:
    > > > Hi List

    >
    > > > I have run into a problem with Quartus synthesis, namely recursive
    > > > intantiation. Don't have the sane issue with Synopsis, AldecHDL or
    > > > Modelsim. Here is a simple example fanout tree (Ashenden - going back
    > > > to basics to figure the issue), but first the Quartus 9.1 message:

    >
    > > > Error (10504): VHDL error at fanout_tree.vhd(58): slice that is
    > > > assigned to target slice has 4 elements, but must have same number of
    > > > elements as target slice (2)

    >
    > > >                    subtree1 : entity work.fanout_tree(recursive)
    > > >                            generic map(
    > > >                                    height  => (height - 1)
    > > >                            )
    > > >                            port map(
    > > >                                    fan_i   => buff_1_s,
    > > >                                    fan_o   => fan_o( (2**(height - 1)) to (2**height) - 1)
    > > >                            );

    >
    > > <snip>

    >
    > > > Can anyone confirm if Quartus is capable of recursive instantiation
    > > > with '93 settings? I'ts going to be a DSP nightmare if not!!

    >
    > > > Best Regards

    >
    > > I've tried recursive instantation in Quartus, and it worked fine.
    > > However I don't think you can use direct instantiation - you must use
    > > component declarations (otherwise how can you instance the component
    > > within itself?)

    >
    > > regards
    > > Alan

    >
    > > --
    > > Alan Fitch- Hide quoted text -

    >
    > > - Show quoted text -

    >
    > Since you only have one architecture (recursive), you do not need to
    > specify the architecture in the direct entity instantiation, just
    > work.fanout_tree.
    >
    > IINM, that way you still don't have to use components/configurations.
    > As long as the entity itself is compiled before the entity (which is
    > required anyway), it should work fine. When you specify the
    > architecture in the entity instantiation, it too must already be
    > compiled.
    >
    > Andy- Hide quoted text -
    >
    > - Show quoted text -


    Umm, as long as the entity is compiled before the ARCHITECTURE (which
    is required anyway)...

    Andy
    Andy, Dec 8, 2009
    #3
  4. dgreig

    KJ Guest

    On Dec 7, 2:40 pm, dgreig <> wrote:

    >
    > Can anyone confirm if Quartus is capable of recursive instantiation
    > with '93 settings? I'ts going to be a DSP nightmare if not!!
    >


    Yes recursive instantiation works. In your case, it was choking on
    the port map assignments of 'fan_o'...
    fan_o => fan_o(0 to (2**(height - 1)) - 1)
    fan_o => fan_o( (2**(height - 1)) to (2**height) - 1)

    The work around is to define new vectors that are of the correct size
    for the entity to be instantiated as such...

    g_tree : if (height > 0) generate
    ....
    signal fan_o_hm1: std_logic_vector(0 to (2**(height - 1)) - 1);
    signal fan_o_hm2: std_logic_vector((2**(height - 1)) to (2**height)
    - 1);

    And then use the new signal in the port map like this...

    subtree0 : entity work.fanout_tree(recursive)
    generic map(
    height => (height - 1)
    )
    port map(
    fan_i => buff_0_s,
    fan_o => fan_o_hm1--OLD==> fan_o(0 to (2**(height - 1)) -
    1)
    );
    subtree1 : entity work.fanout_tree(recursive)
    generic map(
    height => (height - 1)
    )
    port map(
    fan_i => buff_1_s,
    fan_o => fan_o_hm2--OLD==> fan_o( (2**(height - 1)) to
    (2**height) - 1)
    );

    And lastly, hooking up the new vectors to the ports of the entity like
    this...
    fan_o(fan_o_hm1'range) <= fan_o_hm1;
    fan_o(fan_o_hm2'range) <= fan_o_hm2;

    If you think the required work around is a bug in Quartus, you should
    submit a test case to Altera.

    Kevin Jennings
    KJ, Dec 9, 2009
    #4
  5. dgreig

    KJ Guest

    On Dec 7, 6:46 pm, Alan Fitch <> wrote:
    > dgreig wrote:
    > > Hi List

    >
    > > I have run into a problem with Quartus synthesis, namely recursive
    > > intantiation. Don't have the sane issue with Synopsis, AldecHDL or
    > > Modelsim. Here is a simple example fanout tree (Ashenden - going back
    > > to basics to figure the issue), but first the Quartus 9.1 message:

    >
    > > Error (10504): VHDL error at fanout_tree.vhd(58): slice that is
    > > assigned to target slice has 4 elements, but must have same number of
    > > elements as target slice (2)

    >
    > >                    subtree1 : entity work.fanout_tree(recursive)
    > >                            generic map(
    > >                                    height  => (height - 1)
    > >                            )
    > >                            port map(
    > >                                    fan_i   => buff_1_s,
    > >                                    fan_o   => fan_o( (2**(height - 1)) to (2**height) - 1)
    > >                            );

    >
    > <snip>
    >
    > > Can anyone confirm if Quartus is capable of recursive instantiation
    > > with '93 settings? I'ts going to be a DSP nightmare if not!!

    >
    > > Best Regards

    >
    > I've tried recursive instantation in Quartus, and it worked fine.
    > However I don't think you can use direct instantiation - you must use
    > component declarations (otherwise how can you instance the component
    > within itself?)
    >


    @Alan: Direct instantiation works just fine with the OP's code,
    component declarations are not needed.

    @Andy: The specification of the specific architecture to use works
    just fine with the OP's code so even though only one architecture is
    posted, it would work just fine if the entity had several
    architectures and the desired one was not the last one compiled.

    So, even though the OP is recursive, there are no special rules
    required here in regards to instantiating the recursive entity or
    selecting an architecture to use. The only Quartus hiccup was on the
    mapping of a vector slice to a port on the recursively instantiated
    entity.

    Kevin Jennings
    KJ, Dec 9, 2009
    #5
  6. dgreig

    Andy Guest

    I'd had experiences in the past where an architecture would not
    compile if it contained an entity & architecture instantiation for
    which the architecture did not yet exist. Since this is a recursive
    architecture, it would not compile until it had been compiled, and...

    Maybe/apparentlly that has changed?

    Andy
    Andy, Dec 9, 2009
    #6
  7. dgreig

    dgreig Guest

    On Dec 9, 8:21 pm, Andy <> wrote:
    > I'd had experiences in the past where an architecture would not
    > compile if it contained an entity & architecture instantiation for
    > which the architecture did not yet exist. Since this is a recursive
    > architecture, it would not compile until it had been compiled, and...
    >
    > Maybe/apparentlly that has changed?
    >
    > Andy


    As Kevin figured, it was the generic that Quartus was not resolving
    correctly. Here is code that Quartus can handle:

    --
    ===============================================================================================================--
    -- This document is the property of David Greig. The
    document (or any part of it) must not be copied without permission
    from David Greig. --
    -- Any authorised copies of this document
    shall include this header. Copyright © 2009 David
    Greig --
    -------------------------------------------------------------------------------------------------------------------
    -- File : fanout_tree.vhd
    -- Author : David Greig
    --
    -- Description :
    -------------------------------------------------------------------------------------------------------------------
    -- Notes :
    -------------------------------------------------------------------------------------------------------------------
    -- Dependencies :
    --
    ===============================================================================================================--
    library IEEE;
    use IEEE.std_logic_1164.all;
    --
    ===============================================================================================================--
    entity fanout_tree is
    generic(
    height : natural
    );
    port(
    fan_i : in std_logic;
    fan_o : out std_logic_vector( (2**height) - 1 downto 0 )
    );
    end entity fanout_tree;
    --
    ===============================================================================================================--

    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--
    architecture recursive of fanout_tree is
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--
    -------------------------------------------------------------------------------------------------------------------
    begin
    -------------------------------------------------------------------------------------------------------------------
    g_buff : if (height = 0) generate
    fan_o(0) <= fan_i;
    end generate g_buff;
    ----------------------------------------
    g_tree : if (height > 0) generate
    signal buff_s : std_logic_vector(1 downto 0);
    signal fan0_s : std_logic_vector( ((2**(height - 1)) - 1) downto
    0 );
    signal fan1_s : std_logic_vector( ((2**height) - 1) downto (2**
    (height - 1)) );
    begin
    buff : entity work.buf_fan(rtl)
    generic map(
    fanout => 2
    )
    port map(
    fan_i => fan_i,
    fan_o => buff_s
    );
    ----------------------------------------
    subtree0 : entity work.fanout_tree(recursive)
    generic map(
    height => (height - 1)
    )
    port map(
    fan_i => buff_s(0),
    fan_o => fan0_s
    );
    ----------------------------------------
    subtree1 : entity work.fanout_tree(recursive)
    generic map(
    height => (height - 1)
    )
    port map(
    fan_i => buff_s(1),
    fan_o => fan1_s
    );
    ----------------------------------------
    fan_o(fan0_s'range) <= fan0_s;
    fan_o(fan1_s'range) <= fan1_s;
    end generate g_tree;
    -------------------------------------------------------------------------------------------------------------------
    end architecture recursive;
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--

    -- component fanout_tree is
    -- generic(
    -- height : natural
    -- );
    -- port(
    -- fan_i : in std_logic;
    -- fan_o : out std_logic_vector( (2**height) - 1 downto 0 )
    -- );
    -- end component fanout_tree;

    -- i_ : fanout_tree
    -- generic map(
    -- height =>
    -- )
    -- port map(
    -- fan_i =>
    -- fan_o =>
    -- );

    --
    ===============================================================================================================--
    -- This document is the property of David Greig. The
    document (or any part of it) must not be copied without permission
    from David Greig. --
    -- Any authorised copies of this document
    shall include this header. Copyright © 2009 David
    Greig --
    -------------------------------------------------------------------------------------------------------------------
    -- File : buf_fan.vhd
    -- Author : David Greig
    --
    -- Description :
    -------------------------------------------------------------------------------------------------------------------
    -- Notes :
    -------------------------------------------------------------------------------------------------------------------
    -- Dependencies :
    --
    ===============================================================================================================--
    library IEEE;
    use IEEE.std_logic_1164.all;
    --
    ===============================================================================================================--
    entity buf_fan is
    generic(
    fanout : natural
    );
    port(
    fan_i : in std_logic;
    fan_o : out std_logic_vector(fanout - 1 downto 0)
    );
    end entity buf_fan;
    --
    ===============================================================================================================--

    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--
    architecture rtl of buf_fan is
    -------------------------------------------------------------------------------------------------------------------
    attribute keep : boolean; -- Prevents minimizing or removing a
    particular net during combinational logic optimization
    -------------------------------------------------------------------------------------------------------------------
    signal fan_s : std_logic_vector(fanout - 1 downto 0); attribute keep
    of fan_s : signal is true;
    -------------------------------------------------------------------------------------------------------------------
    begin
    -------------------------------------------------------------------------------------------------------------------
    g_fan : for idx in fan_s'range generate
    fan_s(idx) <= fan_i;
    end generate g_fan;
    -------------------------------------------------------------------------------------------------------------------
    fan_o <= fan_s;
    -------------------------------------------------------------------------------------------------------------------
    end architecture rtl;
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--

    By changing the way the genirc height is compared a reducing tree can
    also be realised.

    Best Regards

    David Greig
    dgreig, Dec 10, 2009
    #7
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