Register Files for synthesis

Discussion in 'VHDL' started by Mohammed A khader, Apr 30, 2005.

  1. Hi all,

    I need to synthesize a Register file with 1 synchronous Input Write
    and 2 asynchoronous Output Read . First Output 'Data_Out1' must be
    connected to all the registers (16 here) but second Output
    'Data_Out2' needs to be connected to only last 4 registers ( 12 to 15
    ). This is to reduce the complexity and 2 bits for addressing the
    Data_Out2 port.
    To attain this offset I added '12' to the address of the second
    output.
    Data2_Out <= Regfile_Coff(TO_INTEGER(addrs2_Out)+12);

    Code is given below..


    When I synthesize this using synplicity it is creating 2 register
    files one for each port . Later during mapping it is removing the 4
    registers from one of the register file. But at the end still it has 2
    differnt register files.

    Please give me some suggestion to fix this.
    Thank you.



    entity Coff_Regfile is
    port(
    Data_In : in WORD; -- Input Data
    Addrs_In : in unsigned(3 downto 0); -- Input Address
    Addrs1_Out : in unsigned(3 downto 0); -- Output Address 1
    Addrs2_Out : in unsigned(1 downto 0); -- Output Address 2
    Coff_Wr : in std_logic; -- Write Enable
    Clk : in std_logic; -- Global Clk
    Reset : in std_logic; -- Global Reset

    Data1_Out : out WORD; -- Output Data 1
    Data2_Out : out WORD -- Output Data 2
    );
    end entity Coff_Regfile;

    architecture Coff_Regfile_Arch of Coff_Regfile is
    type Regfile is array (natural range<>) of WORD;
    signal Regfile_Coff : Regfile(0 to 15);
    begin
    --------------------------------------------------------
    -- Concurrent Statements

    -- Regfile_Read Assignments
    Data1_Out <= Regfile_Coff(TO_INTEGER(Addrs1_Out));
    Data2_Out <= Regfile_Coff(TO_INTEGER(addrs2_Out)+12);
    --------------------------------------------------------
    -- Sequential Process
    -- Register File Write Process
    Regfile_Write:process(Clk,Reset)
    begin
    if(Reset = '0')then
    Regfile_Coff <= (others =>(others => '0'));
    elsif(RISING_EDGE(Clk))then
    if(Coff_Wr = '1')then
    Regfile_Coff(TO_INTEGER(Addrs_In)) <= Data_In;
    end if;
    end if;

    end process Regfile_Write;
    --------------------------------------------------------
    end architecture Coff_Regfile_Arch;
    Mohammed A khader, Apr 30, 2005
    #1
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  2. HI,

    Sorry, It was my mistake in interpreting the result from schematic .
    I rectified the mistake. synplicity has synthezied it as logic.
    Mohammed A khader, May 2, 2005
    #2
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