Representing signed numbers in VHDL

Discussion in 'VHDL' started by Kingsley Oteng, May 4, 2004.

  1. is their standard way to represent signed numbers in binary? I know there is
    two's complement notation etc etc. but is there a general standard to do
    this in binary notation or do people tend to use two's complement?

    - Kingsley
    Kingsley Oteng, May 4, 2004
    #1
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