ROM Initialization for Spartan with Synplify

Discussion in 'VHDL' started by jmcoreymv, May 27, 2010.

  1. jmcoreymv

    jmcoreymv

    Joined:
    May 27, 2010
    Messages:
    1
    Likes Received:
    0
    I'm trying to figure out if there's a way to write VHDL code that can initialize a ROM targeting a block ram inside a Xilinx Spartan 3/6 series FPGA. Synthesis would be done through Synplify Pro. According to the Synplify manual, it seems ROM inference with initialization only works for the Virtex FPGAs? Right now I'm using coregen but it has become very tedious since I have about 10 cores I need to generate from .COE files.
     
    jmcoreymv, May 27, 2010
    #1
    1. Advertisements

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Kot

    Is it a bug of synplify?

    Kot, Aug 27, 2003, in forum: VHDL
    Replies:
    3
    Views:
    900
  2. MM
    Replies:
    3
    Views:
    1,517
  3. Pierre-Louis

    Synplify VHDL & Tcl

    Pierre-Louis, Oct 15, 2003, in forum: VHDL
    Replies:
    5
    Views:
    3,672
    Allan Herriman
    Oct 16, 2003
  4. Andrew Hall

    Synplify Clock Rate Question

    Andrew Hall, Apr 12, 2004, in forum: VHDL
    Replies:
    0
    Views:
    1,791
    Andrew Hall
    Apr 12, 2004
  5. Pierre-Louis

    Synplify to Quartus IO standard

    Pierre-Louis, Mar 14, 2005, in forum: VHDL
    Replies:
    3
    Views:
    1,120
    Mike Treseler
    Mar 14, 2005
  6. Mohammed A Khader

    Synplify warning CL209

    Mohammed A Khader, Apr 27, 2005, in forum: VHDL
    Replies:
    4
    Views:
    962
    Ken McElvain
    Apr 28, 2005
  7. hangeonos
    Replies:
    0
    Views:
    1,009
    hangeonos
    May 24, 2009
  8. dkbauter
    Replies:
    1
    Views:
    2,637
    dkbauter
    Aug 4, 2009
Loading...