Same entity name in different libraries

Discussion in 'VHDL' started by Steven Kauffmann, Nov 21, 2007.

  1. Hi,

    Is it possible to write two components with the same entity name but
    associated in an other library?

    For example: I have an entity called multiplier but one multiplier is
    an unsigned multiplier and associated with the unsigned_multiplier
    library and there is a signed multiplier associated with the
    signed_multiplier library.

    The architecture of my top file should look like this:

    unsig_mult: entity unsigned_multiplier_lib.multiplier
    port map(...);

    sig_mult: entity signed_multiplier_lib.multiplier
    port map(...);

    Is it possible to write something like this?

    Regards

    Steven
    Steven Kauffmann, Nov 21, 2007
    #1
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  2. On Wed, 21 Nov 2007 07:13:04 -0800 (PST), Steven Kauffmann
    <> wrote:

    >unsig_mult: entity unsigned_multiplier_lib.multiplier
    > port map(...);
    >
    >sig_mult: entity signed_multiplier_lib.multiplier
    > port map(...);
    >
    >Is it possible to write something like this?


    Fine.

    Don't forget to add

    library signed_multiplier_lib;
    library unsigned_multiplier_lib;

    just before your top-level entity.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Nov 21, 2007
    #2
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  3. On Nov 21, 4:31 pm, Jonathan Bromley <>
    wrote:
    > On Wed, 21 Nov 2007 07:13:04 -0800 (PST), Steven Kauffmann
    >
    > <> wrote:
    > >unsig_mult: entity unsigned_multiplier_lib.multiplier
    > > port map(...);

    >
    > >sig_mult: entity signed_multiplier_lib.multiplier
    > > port map(...);

    >
    > >Is it possible to write something like this?

    >
    > Fine.
    >
    > Don't forget to add
    >
    > library signed_multiplier_lib;
    > library unsigned_multiplier_lib;
    >
    > just before your top-level entity.
    >


    If I create such a project in ISE I get this warning:

    WARNING:projectMgmt - "/tmp/xilinx_lib/unsigned_lib/multiplier.vhd"
    line 7 duplicate design unit: 'Entity|multiplier'
    WARNING:projectMgmt - "/tmp/xilinx_lib/unsigned_lib/multiplier.vhd"
    line 16 duplicate design unit: 'Architecture|multiplier|rtl'

    And only the signed_multiplier core is used.

    Any idea how to fix this?

    Steven
    Steven Kauffmann, Nov 22, 2007
    #3
  4. On Thu, 22 Nov 2007 00:28:42 -0800 (PST),
    Steven Kauffmann <> wrote:

    >If I create such a project in ISE I get this warning:
    >
    >WARNING:projectMgmt - "/tmp/xilinx_lib/unsigned_lib/multiplier.vhd"
    >line 7 duplicate design unit: 'Entity|multiplier'
    >WARNING:projectMgmt - "/tmp/xilinx_lib/unsigned_lib/multiplier.vhd"
    >line 16 duplicate design unit: 'Architecture|multiplier|rtl'
    >
    >And only the signed_multiplier core is used.
    >
    >Any idea how to fix this?


    No. This is something that happens when you first load
    the project, before you try to synthesize it, yes? If
    I'm right about that, then it's ISE's idiotic machinery
    that does a rough-and-ready parse of all the HDL sources
    to decide what the hierarchy looks like *before* doing
    a proper synthesis. Quartus does something equally
    brainless, or at least it did the last time I looked.
    These half-baked automatic hierarchy inference things
    are an invention of the devil - they completely screw
    any attempt to do anything interesting with configuration
    (like yours), or recursive instantiation (see various
    earlier threads here), or creative uses of "generate".

    With luck, it's just a warning. If you manually set the
    top-level entity for XST to synthesize, you will probably
    find that the rest of the flow works OK.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Nov 22, 2007
    #4
  5. On Nov 22, 9:51 am, Jonathan Bromley <>
    wrote:
    > On Thu, 22 Nov 2007 00:28:42 -0800 (PST),
    >
    > Steven Kauffmann <> wrote:
    > >If I create such a project in ISE I get this warning:

    >
    > >WARNING:projectMgmt - "/tmp/xilinx_lib/unsigned_lib/multiplier.vhd"
    > >line 7 duplicate design unit: 'Entity|multiplier'
    > >WARNING:projectMgmt - "/tmp/xilinx_lib/unsigned_lib/multiplier.vhd"
    > >line 16 duplicate design unit: 'Architecture|multiplier|rtl'

    >
    > >And only the signed_multiplier core is used.

    >
    > >Any idea how to fix this?

    >
    > No. This is something that happens when you first load
    > the project, before you try to synthesize it, yes?


    Yes correct but this warning changes into an error while synthesizing.

    > I'm right about that, then it's ISE's idiotic machinery
    > that does a rough-and-ready parse of all the HDL sources
    > to decide what the hierarchy looks like *before* doing
    > a proper synthesis. Quartus does something equally
    > brainless, or at least it did the last time I looked.
    > These half-baked automatic hierarchy inference things
    > are an invention of the devil - they completely screw
    > any attempt to do anything interesting with configuration
    > (like yours), or recursive instantiation (see various
    > earlier threads here), or creative uses of "generate".
    >
    > With luck, it's just a warning. If you manually set the
    > top-level entity for XST to synthesize, you will probably
    > find that the rest of the flow works OK.


    When synthezising I get this error:

    ERROR:HDLParsers:3317 - "/tmp/xilinx_lib/top.vhd" Line 6. Library
    sig_lib cannot be found.
    ERROR:HDLParsers:3014 - "/tmp/xilinx_lib/top.vhd" Line 7. Library unit
    sig_lib is not available in library work.

    If I delete the other library(unsig_lib) than I don't get this error.
    Only when both libraries are used I get this error.

    I'm using the webedition of ISE maybe this version of ISE isn't that
    sophisticated?

    Steven
    Steven Kauffmann, Nov 22, 2007
    #5
  6. On Thu, 22 Nov 2007 00:28:42 -0800 (PST), Steven Kauffmann
    <> wrote:

    >On Nov 21, 4:31 pm, Jonathan Bromley <>
    >wrote:
    >> On Wed, 21 Nov 2007 07:13:04 -0800 (PST), Steven Kauffmann
    >>
    >> <> wrote:
    >> >unsig_mult: entity unsigned_multiplier_lib.multiplier
    >> > port map(...);

    >>
    >> >sig_mult: entity signed_multiplier_lib.multiplier
    >> > port map(...);

    >>
    >> >Is it possible to write something like this?

    >>
    >> Fine.
    >>
    >> Don't forget to add
    >>
    >> library signed_multiplier_lib;
    >> library unsigned_multiplier_lib;
    >>
    >> just before your top-level entity.
    >>

    >
    >If I create such a project in ISE I get this warning:
    >
    >WARNING:projectMgmt - "/tmp/xilinx_lib/unsigned_lib/multiplier.vhd"
    >line 7 duplicate design unit: 'Entity|multiplier'
    >WARNING:projectMgmt - "/tmp/xilinx_lib/unsigned_lib/multiplier.vhd"
    >line 16 duplicate design unit: 'Architecture|multiplier|rtl'
    >
    >And only the signed_multiplier core is used.
    >
    >Any idea how to fix this?


    in ISE as of 7.1 onwards, the synthesis tool XST itself actually works
    correctly, (at least, with the correct component selected in embedded
    configuration statements; I don't know about external configurations or
    direct instantiation) but there seem to be different GUI bugs in each
    ISEversion, regarding the same component name in different libraries.

    In 9.1, by persisting adding source files and moving them to the correct
    libraries I eventually got them both visible to XST, but the GUI never
    ever displayed them both properly... ( I THINK I needed to add the
    second to "work", move it to its lib, delete the first, re-add it and
    move it , but...)

    As of August a CR was filed to fix that bug in some unstated future
    version; I guess we'll wait and see.

    I gave up and used different names in the end.

    - Brian
    Brian Drummond, Nov 22, 2007
    #6
  7. Steven Kauffmann

    Andy Guest

    On Nov 21, 9:31 am, Jonathan Bromley <>
    wrote:
    > On Wed, 21 Nov 2007 07:13:04 -0800 (PST), Steven Kauffmann
    >
    > <> wrote:
    > >unsig_mult: entity unsigned_multiplier_lib.multiplier
    > > port map(...);

    >
    > >sig_mult: entity signed_multiplier_lib.multiplier
    > > port map(...);

    >
    > >Is it possible to write something like this?

    >
    > Fine.
    >
    > Don't forget to add
    >
    > library signed_multiplier_lib;
    > library unsigned_multiplier_lib;
    >
    > just before your top-level entity.
    > --
    > Jonathan Bromley, Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
    >
    > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
    > ://www.MYCOMPANY.com
    >
    > The contents of this message may contain personal views which
    > are not the views of Doulos Ltd., unless specifically stated.


    It would be preferable to reference the library at the top of the
    architecture, not the entity, that instantiates the multiplier. It
    will work either way, but since the entity itself does not need the
    library, it should not reference it.

    Andy
    Andy, Nov 26, 2007
    #7
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