Selecting generic at simulation time.

Discussion in 'VHDL' started by Niv (KP), Oct 31, 2009.

  1. Niv (KP)

    Niv (KP) Guest

    I have a testbench which reads data from a memory, which is
    initialised with data from a file, the file name is a generic in the
    memory model.

    Is there some way to start the simulation which then asks which file
    I'd like to use to initialise the memory before the sim progresses?
    TIA, Niv.
     
    Niv (KP), Oct 31, 2009
    #1
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  2. Niv (KP)

    Pontus Guest

    You can also use environment variables when opening a file.
    I've succeded both with aldecs and mentors vhdl simulators,
    use $$MY_ENV_VAR for riviera, use $MY_ENV_VAR for modelsim.

    So something similar to this should work (can' test my self right now)
    file_open(status, "$$MY_PATH/my_file.ext", L.all, READ_MODE);

    HTH -- Pontus
     
    Pontus, Oct 31, 2009
    #2
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  3. Niv (KP)

    Andy Guest

    If the file is opened/read dynamically in a process, then you cannot
    initialize the memory array via its declaration. With a generic, you
    can initialize the array declaration with a function call that uses
    the generic, opens the file, reads the data and returns an initialized
    array. This initialization is done during the VHDL elaboration phase,
    which is "hidden" at the beginning of many simulators (before the
    actual simulation starts), but is an explicit step on others (e.g.
    Cadence).

    Andy
     
    Andy, Nov 2, 2009
    #3
  4. Niv (KP)

    logic_guy Guest

    I've also written testbenches that pause and wait for the user to source
    a tcl script. The tcl script sets a VHDL variable (using the "change"
    command in Modelsim), issues a "force" command on a signal to trigger an
    event, and that starts a process that does some massaging of the
    variable (mainly to determine to number of non-blank characters) and
    feeds that to a VHDL open statement to open the requested file.

    Charles Bailey
     
    logic_guy, Dec 30, 2009
    #4
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