Simulating Inverted Registers

Discussion in 'VHDL' started by Shannon, Jun 30, 2009.

  1. Shannon

    Shannon Guest

    Seems like I'm posting a lot lately. I really appreciate all the help
    you guys have given. You are helping bring me up to speed quickly.
    On to the question....

    Although my question is about simulation, this concerns a design for
    synthesis.

    I have a 32-bit register that I load a default value into during
    reset. As Altera has explained to me, the hardware can only pre-load
    zeros. To get a '1' bit they put inverters on each side of the flip-
    flop and force it clear. Ok I get that.

    In actuality the "inverters" don't really exist. They get pushed into
    the surrounding logic. So when I simulate using Quartus's simulator
    or ModelSim I probe my register and I get some inverted bits.
    (corresponding to where the ones are in my default value).

    I've tested the real hardware and it works fine. I know I'm not the
    first person to load a default value into a register. Is there a
    "standard" way of dealing with this in simulation? I have lots of
    ideas but they all seem kludge-y. I suspect there is some common ways
    of dealing with it.

    I hope I've explained the situation clear enough.

    Thanks,
    Shannon
    Shannon, Jun 30, 2009
    #1
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  2. Shannon

    Shannon Guest

    On Jun 30, 1:48 pm, Shannon <> wrote:
    > Seems like I'm posting a lot lately.  I really appreciate all the help
    > you guys have given.  You are helping bring me up to speed quickly.
    > On to the question....
    >
    > Although my question is about simulation, this concerns a design for
    > synthesis.
    >
    > I have a 32-bit register that I load a default value into during
    > reset.  As Altera has explained to me, the hardware can only pre-load
    > zeros.  To get a '1' bit they put inverters on each side of the flip-
    > flop and force it clear.  Ok I get that.
    >
    > In actuality the "inverters" don't really exist.  They get pushed into
    > the surrounding logic.  So when I simulate using Quartus's simulator
    > or ModelSim I probe my register and I get some inverted bits.
    > (corresponding to where the ones are in my default value).
    >
    > I've tested the real hardware and it works fine.  I know I'm not the
    > first person to load a default value into a register.  Is there a
    > "standard" way of dealing with this in simulation?  I have lots of
    > ideas but they all seem kludge-y.  I suspect there is some common ways
    > of dealing with it.
    >
    > I hope I've explained the situation clear enough.
    >
    > Thanks,
    > Shannon


    Here is a complete entity that simulates what I'm talking about:

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.numeric_std.ALL;

    entity inverted is
    port
    (
    reset : in std_logic;
    clk : in std_logic;
    byte_out : out std_logic_vector(7 downto 0)
    );
    end inverted;

    architecture rtl of inverted is

    signal byte : unsigned(7 downto 0);

    begin

    process(clk, reset)
    begin
    if reset = '1' then
    byte <= X"42"; --arbitrary number for example
    elsif rising_edge(clk) then
    byte <= byte + 1;
    end if;
    end process;

    byte_out <= std_logic_vector(byte);

    end rtl;

    In this example byte_out will simulate exactly as you would expect -
    starting off at 42h and counting up each clock. "byte" however will
    not simulate as you would expect. Well at least not how "I" would
    expect. lol

    Shannon
    Shannon, Jun 30, 2009
    #2
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  3. Shannon

    Andy Guest

    You could reset to zeroes, then synchronously load your default value
    on the first clock. That may even take less logic than inverting/
    uninverting the bits in some cases.

    There are lots of times where RTL vs post-S/P&R models don't match,
    such as enumerated types, etc., but not many good tricks for dealing
    with it, except to avoid it (i.e. use a self-checking testbench, not
    just one that dumps a lot of signals to a waveform for you to check
    manually). Assuming "byte" comes out on a port somewhere that the TB
    can access it, it should have the same semantics there as your RTL,
    even if it is a gate level model.

    Andy
    Andy, Jun 30, 2009
    #3
  4. Shannon wrote:
    > Seems like I'm posting a lot lately. I really appreciate all the help
    > you guys have given. You are helping bring me up to speed quickly.
    > On to the question....
    >
    > Although my question is about simulation, this concerns a design for
    > synthesis.
    >
    > I have a 32-bit register that I load a default value into during
    > reset. As Altera has explained to me, the hardware can only pre-load
    > zeros. To get a '1' bit they put inverters on each side of the flip-
    > flop and force it clear. Ok I get that.


    Device registers without a direct asynchronous preset
    may not handle both an asynchronous *and* synchronous preset
    to the same value.

    I ran into a case once where a cyclic synchronous preset
    of a 32 bit register would not route with
    an asynchronous preset to the same value.

    I expect that an asynchronous reset to zero would have worked,
    but I didn't try that at the time.

    -- Mike Treseler
    Mike Treseler, Jul 1, 2009
    #4
  5. On 30 Jun., 23:04, Shannon <> wrote:
    > > the surrounding logic.  So when I simulate using Quartus's simulator
    > > or ModelSim I probe my register and I get some inverted bits.
    > > (corresponding to where the ones are in my default value).


    >         if reset = '1' then
    >                 byte <= X"42";  --arbitrary number for example

    [..]
    > byte_out <= std_logic_vector(byte);

    [..]
    > In this example byte_out will simulate exactly as you would expect
    > starting off at 42h and counting up each clock.  "byte" however will
    > not simulate as you would expect.  Well at least not how "I" would
    > expect. lol


    If you mean that the netlist simulation shows you "inverted" registers
    for some bits than you have a normal result for synthesis over
    boundaries of ff. A inverter after the FF output is just moved in
    front of the FF with inverting even reset case.

    In fact this is no problem of functionality but of verification as you
    need information from your tool which FF is inverted. This is less a
    problem for FPGA but a real pain for an ASIC when it comes to formal
    verification or ASIC test with dedicated scanpattern.

    bye Thomas
    Thomas Stanka, Jul 1, 2009
    #5
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