simulation help

Discussion in 'VHDL' started by vibs, Aug 12, 2004.

  1. vibs

    vibs Guest

    Hi to all
    I am at the learner level of VHDL ,I am making an encoder for audio
    signals.I want to know ,how to test my design for audio signals .Means how
    can i give data for simulation.Is there any way to get binary format of
    audio files.

    please give me some hint.
    thanks

    vibs
     
    vibs, Aug 12, 2004
    #1
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  2. Mike Treseler, Aug 12, 2004
    #2
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