Start statemachine without clock

[otis]

Hi,
I have a state machine. In a particular state the system goes to power save mode where the clock will be stopped.

At this state the state machine looking for an external signal, when It gets the statemachine sends a signal to analog block to start the clock and when it get the clock it will continue the state machine.

How this particular state can be done?

the design will be done in Verilog

Any input are highly appreciated.

 

[debayan_p]

Well there is an easier way I guess.........I don't know whether it will serve your purpose!

Use an external gated-clock for your design! For this you need not invoke the analog unit; the clk generator will always be ON. You SM can recover from power saving mode when the external stimulus/signal is received. This ext. signal & the clock signals needs to be fed to the SM block via an AND gate.

 

[otis]

Switching off the clock is also for power save.

My question is the state machine is synchronous but in power save mode it should wakeup for asynchronous signal. How do make the SM to react on this signal without clock.