I2C START STOP generation

Discussion in 'VHDL' started by VIPS, Jul 18, 2010.

  1. VIPS

    VIPS Guest

    Hi All

    I am implementing an I2C slave and low level interface to interface it
    to EEPROM. I am using I2c Master for verifying this module . The I2C
    Master code is reused from some other module. He has implemented the
    I2C in a fashion that the PULL up and the Pull Down is to be provided
    from outside. It has SCL_IN,SCL_OUT, SDA_IN,SDA_OUT ports and some
    other control signals. It doesnot generate a start and stop condition
    inside i2c master block. I have seen the code it waits for the SDA to
    go from LOW to HIGH .My question is

    1. in I2C master do we have to make a separate module in verilog ( the
    code is in verilog) to generate start and stop condition. or it is
    expected to have this functionality inside the I2C master
    controller.
    2. How do I connect for verifying the slave and the Interface . The
    SDA_IN( master) is connected to SDA_OUT( slave) and SCL_IN( master) is
    connects to SCL_GEN module ( as the I2C master takes SCL_IN as inut to
    the master module . SCL_OUT(master) connects to SCL_IN (SLAVE),
    SDA_OUT( master) to SDA_IN( slave) . The confusion is the start and
    stop generation /detection module as it is not inside the controller
    has to be connected from outside. Will the START gen module just send
    SCL and SDA to I2c Master for start operation and the the master will
    take from there.
    3. In the initial state when it is reset under normal protocol
    situation the SCL is Z and the SDA is Z both pulled up . To start the
    operation for a start gen condition is there a separate module to do
    so .How normally in I2C master it is done( someone who has already
    done it.
    4. I have gone througn the standard but got confused as how the first
    start and stop condition is generated and who will toggle the first
    SDA low to high.

    I have googled also and looked for some reference designs but it is
    not running well in sumulation to understand how the first start
    operation is gereated as the slave is IDLE and waiting for the start
    signal from the master.

    I would highly appreciate any suggestions on this issue.

    Thanks in advance

    Vipul
    VIPS, Jul 18, 2010
    #1
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  2. VIPS wrote:

    > Hi All
    >
    > I am implementing an I2C slave and low level interface to interface it
    > to EEPROM. I am using I2c Master for verifying this module . The I2C
    > Master code is reused from some other module. He has implemented the
    > I2C in a fashion that the PULL up and the Pull Down is to be provided
    > from outside. It has SCL_IN,SCL_OUT, SDA_IN,SDA_OUT ports and some
    > other control signals. It doesnot generate a start and stop condition
    > inside i2c master block. I have seen the code it waits for the SDA to
    > go from LOW to HIGH .My question is
    >
    > 1. in I2C master do we have to make a separate module in verilog ( the


    This is a VHDL group, not Verilog. Besides, I do not see any VHDL or Verilog
    related question. Just architectural issues, not related to the language in
    which the blocks are designed.

    > code is in verilog) to generate start and stop condition. or it is
    > expected to have this functionality inside the I2C master
    > controller.


    The latter would be most logical. I cannot think of any reason why the
    start/stop patterns should be generated by a separate block.

    > 2. How do I connect for verifying the slave and the Interface . The
    > SDA_IN( master) is connected to SDA_OUT( slave) and SCL_IN( master) is
    > connects to SCL_GEN module ( as the I2C master takes SCL_IN as inut to
    > the master module . SCL_OUT(master) connects to SCL_IN (SLAVE),
    > SDA_OUT( master) to SDA_IN( slave) . The confusion is the start and
    > stop generation /detection module as it is not inside the controller
    > has to be connected from outside. Will the START gen module just send
    > SCL and SDA to I2c Master for start operation and the the master will
    > take from there.


    This whole thing with a separate start/stop generation block only makes
    things over complicated. Get rid of it.

    > 3. In the initial state when it is reset under normal protocol
    > situation the SCL is Z and the SDA is Z both pulled up . To start the
    > operation for a start gen condition is there a separate module to do
    > so .How normally in I2C master it is done( someone who has already
    > done it.
    > 4. I have gone througn the standard but got confused as how the first
    > start and stop condition is generated and who will toggle the first
    > SDA low to high.


    The first transition in SDA is from high to low, while SCL is high. That
    transition is generated by the master.

    For more information, see for example http://en.wikipedia.org/wiki/I²C
    and the references there to the official I2C specifications.

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
    Paul Uiterlinden, Jul 22, 2010
    #2
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