State machine difficulties

[better_cs_now]

Hello all,

I'm having difficulties with the code below on my Spartan 3.

I've created an 8-bit RAM with 256 locations. It has the following
inputs:
wr_en
addr
data_in

My goal is to write the numbers 1 - 4 to addresses 1 - 4 of the RAM
(and then read them back).

In the code below, I never get out of the state SETUP_WRITE. I have a
feeling this has something to do with the way I'm using variables (as
opposed to signals), but I just don't see what I'm doing wrong.

In the code below, data_out is tied to some LEDs on my board.

Thanks,
Dave

seq: process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
current_state <= INIT;
else
current_state <= next_state;
end if;
end if;
end process seq;

comb: process(current_state)
variable addr_to_write: natural;
begin
case current_state is
when INIT =>
addr_to_write := 1;
next_state <= SETUP_WRITE;
when SETUP_WRITE =>
wr_en <= '1';
addr <= addr_to_write;
data_in <= std_logic_vector(to_unsigned(addr_to_write, 8));
addr_to_write := addr_to_write + 1;

if (addr_to_write /= 5) then
next_state <= SETUP_WRITE;
else
next_state <= READ_ADDR_1;
end if;
.
.
.

 

[Mike Treseler]

My goal is to write the numbers 1 - 4 to addresses 1 - 4 of the RAM
(and then read them back).

I would do this using simulation, not synthesis.
The problem with designing another hardware
entity to test the ram is that it needs
to be debugged and verified as well.

If you just want to see something on the
scope, instance an UP counter and wire
wr_en to the count LSB Q0,
then data_in to Q1-8, then addr to Q9-17

-- Mike Treseler

 

[jmaniac]

comb: process(current_state)
variable addr_to_write: natural;
begin
case current_state is
when INIT =>
addr_to_write := 1;
next_state <= SETUP_WRITE;
when SETUP_WRITE =>
wr_en <= '1';
addr <= addr_to_write;
data_in <= std_logic_vector(to_unsigned(addr_to_write, 8));
addr_to_write := addr_to_write + 1;

if (addr_to_write /= 5) then
next_state <= SETUP_WRITE;
else
next_state <= READ_ADDR_1;
end if;

Hey.. check up your sensitivity list in the combination logic... I
guess the sensitvity never trigers once it enters SETUP_WRITE state

 

[Al]

comb: process(current_state)
variable addr_to_write: natural;
begin
case current_state is
when INIT =>
addr_to_write := 1;
next_state <= SETUP_WRITE;
when SETUP_WRITE =>
wr_en <= '1';
addr <= addr_to_write;
data_in <= std_logic_vector(to_unsigned(addr_to_write, 8));
addr_to_write := addr_to_write + 1;

if (addr_to_write /= 5) then
next_state <= SETUP_WRITE;
else
next_state <= READ_ADDR_1;
end if;

I think the problem sits on the fact that addr_to_write is inside a
combinational process. Have you tried to simulate the code and check the
behaviour of this variable? To me it will be inferred as a latch rolling
up to the 5, at that point the next_state will go to READ_ADDR_1.
Then you better check the RAM timing specifications, I don't really
understand if changing the addr and data_in when wr_en is active is a
correct way of writing into a ram (but I don't know much of Spartan 3 so
I may be wrong).

Either you include all in a one-process FSM, or you'll have to change
approach moving the addr and the data_in out of the combinational
process and handling them as counters in a sequential one.

Good luck

Al