Synthesis of FSMs..

Discussion in 'VHDL' started by VHDL User, Sep 24, 2004.

  1. VHDL User

    VHDL User Guest

    Hi All,
    Suppose I have a description of a FSM in which I use self defined (enum)
    data type State which can be amongst {"Red","Black","Blue"}.
    Clearly 2 FFs will suffice to describe 3 states.My question is related
    to the synthesis of such a machine:
    1.How does the tool decide the encoding mechanism? I can have 00,01,11 or
    any 3 of 4 options.Is there a way to fix this apriori within VHDL Code
    itself ? How do I otherwise specify my preferences? ( I use Synplicity.)
    2.When would a encoding of 3 states in a 001,010,100 manner be more
    "useful" or "better",if at all? Clearly,more FFs would be needed,but
    would this affect the speed ?
    Thanks a lot,
    Bye
    VHDL User, Sep 24, 2004
    #1
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  2. VHDL User <> wrote:

    :Hi All,
    : Suppose I have a description of a FSM in which I use self defined (enum)
    :data type State which can be amongst {"Red","Black","Blue"}.
    : Clearly 2 FFs will suffice to describe 3 states.My question is related
    :to the synthesis of such a machine:
    :1.How does the tool decide the encoding mechanism? I can have 00,01,11 or
    :any 3 of 4 options.

    A straightforward, general way is like this:

    subtype TSTATE is std_logic_vector(1 downto 0);

    constant RED : TSTATE := "00";
    constant BLACK : TSTATE := "01";
    constant BLUE : TSTATE := "10";

    signal STATE_VARIABLE : TSTATE;

    When you use a case..when to select your state from this, assign the
    "others" case to an illegal-state catcher (eg reset).

    :Is there a way to fix this apriori within VHDL Code
    :itself ? How do I otherwise specify my preferences? ( I use Synplicity.)

    This is called "one hot" encoding. Where to use it is a tradeoff: you
    have more flipflops, but less decoding logic. Typically, one-hots run
    faster than fully decoded states (less logic).
    If you use one-hot, you may need to include safety logic to catch
    cases of two flipflops getting set together (no, it shouldn't happen).

    :2.When would a encoding of 3 states in a 001,010,100 manner be more
    :"useful" or "better",if at all? Clearly,more FFs would be needed,but
    :would this affect the speed ?
    :Thanks a lot,
    :Bye
    David R Brooks, Sep 25, 2004
    #2
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  3. VHDL User

    anupam Guest

    Hi Supreet,

    1.
    If u want to encode in your manner then u have to declare the state as
    constant like as
    constant red : std_logic_vector(1 downto 0) := "00"
    .....
    ....
    2.
    for this you have to assign the state machine in one - hot encoding
    method.Definitely the FFs used will be more and will consume more logic
    but the speed of design will be improved (increased).

    Hope it is helpfull to u .

    Regards,
    Anupam Garg
    anupam, Sep 25, 2004
    #3
  4. VHDL User

    Niv Guest

    One thing we do where I work is to define 2^N states, so that 2^N is always
    greater than the number of states we need,
    so in your case there would be a fourth "spare" state, say "sp_01".

    We would then write the state machine so that it passed through all
    spare states after reset before reaching the "idle" or "start" state.

    We would use binary encoding.

    This forces the synth to produce only N FF's, with all possible states
    declared and used, albeit fleetingly for the spare states.

    This helps with safety critical systems; and testbenches can test that all
    states are exercised.

    Yes, the design will be slower than one-hot (a bit, size dependant I
    suppose).

    Hope that helps, Niv.
    Niv, Sep 25, 2004
    #4
  5. VHDL User

    cristian Guest

    "Niv" <> wrote in message news:<lY95d.238$>...
    > One thing we do where I work is to define 2^N states, so that 2^N is always
    > greater than the number of states we need,
    > so in your case there would be a fourth "spare" state, say "sp_01".
    >
    > We would then write the state machine so that it passed through all
    > spare states after reset before reaching the "idle" or "start" state.
    >
    > We would use binary encoding.
    >
    > This forces the synth to produce only N FF's, with all possible states
    > declared and used, albeit fleetingly for the spare states.
    >
    > This helps with safety critical systems; and testbenches can test that all
    > states are exercised.
    >
    > Yes, the design will be slower than one-hot (a bit, size dependant I
    > suppose).
    >
    > Hope that helps, Niv.


    Dear VHDL_User,

    FSM Synthesis is a complicated subject. To simplify the problem, two
    main subjecst: which architecture you will use to implement your
    design, FPGA or CPLD. Then, which synthesis tool you will use to
    synthesize your code. I am familiar with both Synplify and Leonardo.
    For the number of states you have in your FSM, 3 or 4, there are no
    too many options, both synthesis will use sequential as default, for
    more than 5 states they will use one-hot even though is not the best
    solution for CPLDs. If you want to overwrite the default sequantial
    coding style you will need to use synthesis attributes. As we all know
    this is not good if we are looking for portable designs. Depending on
    the synthesis tool will be the attribute to use. Check the your
    synthesis tool's user guide to find which attribute you need to use.

    best regards,

    cristian
    cristian, Sep 26, 2004
    #5
  6. Niv wrote:
    > We would then write the state machine so that it passed through all
    > spare states after reset before reaching the "idle" or "start" state.
    > We would use binary encoding.
    > This forces the synth to produce only N FF's, with all possible states
    > declared and used, albeit fleetingly for the spare states.



    Interesting.

    Do you do the same sort of thing
    for counters with unused values?


    -- Mike Treseler
    Mike Treseler, Sep 29, 2004
    #6
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