systemC and modelsim

Discussion in 'VHDL' started by goose, Jun 29, 2006.

  1. goose

    goose

    Joined:
    Jun 29, 2006
    Messages:
    4
    hi everyone,

    I am trying to work on systemC in modelsim 6.1 PE. i need to force a user defined value through a .do file making use of proc function. the force command doesn't force values to systemc variables and on using the change comand i get an error saying

    Error: (vsim-3661) Unable to change 'a_i': Invalid target for a value change.

    the command refernce clearly mentions that i can change values for a scalar c variable using change command and i have declared a_i as a variable of type int. still the error shows up. i have switched on the c debug mode as mentioned in the command refernce.

    can some one tell me what am i doing wrong or an alternate way of forcing values to systemc variables.



    -----------------
    Regards
    Goose
    goose, Jun 29, 2006
    #1
    1. Advertising

  2. goose

    goose

    Joined:
    Jun 29, 2006
    Messages:
    4
    code

    i am putting up the code tht i am using to test the thing and also the do file

    code

    //test.cpp

    #include "systemc.h"

    SC_MODULE(test)
    {
    sc_signal <int> a;

    int a_i;

    void prc_test();
    void prc_driver();

    SC_CTOR(test)
    {
    a_i=0;
    a=0;
    SC_METHOD(prc_test);
    SC_THREAD(prc_driver);
    sensitive<<a;
    }
    };

    void test::prc_test()
    {
    cout<<"The value you entered is "<<a;
    }

    void test::prc_driver()
    {
    wait(25,SC_NS);
    a.write((int)a_i);
    }

    SC_MODULE_EXPORT(test);


    do file

    quit -sim

    # Setting the Proj Directory and the working Directory

    set projdir "C:/Modeltech_6.1/Sourabh"

    # Change directory to the simulation directory

    cd $projdir/sim

    # Delete the Initial work file

    file delete -force work

    # Create the work library

    vlib work

    vmap work work

    onbreak {resume}

    sccom -g -work work C:/modeltech_6.1/sourabh/test.cpp
    sccom -link
    vsim test
    add wave a
    add wave a_i
    cdbg debug_on
    proc mov {a_u} {
    change a_i $a_u
    run 100 ns
    }




    -----------------
    Regards
    Goose
    goose, Jun 29, 2006
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Baskar
    Replies:
    0
    Views:
    1,642
    Baskar
    Mar 6, 2006
  2. goose

    systemC and modelsim

    goose, Jun 29, 2006, in forum: C Programming
    Replies:
    1
    Views:
    2,877
    goose
    Jun 29, 2006
  3. Steven Derrien
    Replies:
    2
    Views:
    3,739
    Steven Derrien
    Jul 13, 2006
  4. Mr. Peterfolk

    C-Systemc-VHDL problem in Modelsim

    Mr. Peterfolk, Jan 24, 2007, in forum: VHDL
    Replies:
    3
    Views:
    750
    Mr. Peterfolk
    Jan 25, 2007
  5. doromdor
    Replies:
    0
    Views:
    860
    doromdor
    Nov 17, 2009
Loading...

Share This Page