TestBench problem for ROM table

Discussion in 'VHDL' started by rajan, Jul 24, 2003.

  1. rajan

    rajan Guest

    Dear experts,

    I have made a ROM table in vhdl, and it compiles successfully with Modelsim.
    But, I am not able to simulate the testbench. What am I doing wrong.

    -------------------

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.STD_LOGIC_ARITH.all;
    use IEEE.STD_LOGIC_UNSIGNED.all;

    entity Rom_Table is
    port(
    Ain : in std_logic_vector(3 downto 0);
    Bout : out std_logic_vector(5 downto 0)
    );
    end Rom_Table;

    architecture BEH of Rom_Table is
    begin
    process(Ain)
    constant MEM : NATURAL := 16;
    type TRUTH_TABLE is array (0 to MEM-1) of std_logic_vector(5 downto
    0);
    constant TABLE : TRUTH_TABLE := (
    ('0','0','0','0','0','0'),
    ('0','0','0','0','0','1'),
    ('0','1','0','0','1','1'),
    ('1','1','0','0','1','1'),
    ('0','0','0','0','1','1'),
    ('0','1','1','1','1','1'),
    ('0','0','0','0','0','0'),
    ('0','0','0','0','1','1'),
    ('0','1','1','0','1','1'),
    ('1','1','1','0','1','1'),
    ('0','0','0','0','1','1'),
    ('0','1','1','1','1','1'),
    ('1','1','1','1','1','1')
    ('0','0','0','0','0','0'),
    ('0','0','0','0','1','1'),
    ('0','1','1','0','1','1'),
    );

    begin
    Bout <= TABLE(conv_integer(Ain));
    end process;
    end BEH;
    -----------------

    I have written a TestBench for this as follows. It waits until Ain(3)='1',
    and then starts giving the output.

    ------------------------TB------
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    use std.textio.all;
    USE ieee.numeric_std.ALL;

    LIBRARY work;
    USE work.ALL;

    ENTITY Rom_Table_tb is
    END Rom_Table_tb;

    ARCHITECTURE bench of Rom_Table_tb is
    COMPONENT Rom_Table PORT ( Ain : IN std_logic_vector (3 DOWNTO 0);
    Bout : OUT std_logic_vector (5 DOWNTO 0)
    );
    END COMPONENT;

    SIGNAL Ain : std_logic_vector (3 DOWNTO 0);
    SIGNAL Bout : std_logic_vector (5 DOWNTO 0);
    SIGNAL half_clk : TIME := 100 NS;

    BEGIN

    d1 : Rom_Table PORT MAP (Ain, Bout);

    ---------------------------------------------------------------------------
    ----
    -- Read stimulus from text file "stimulus.txt"
    ---------------------------------------------------------------------------
    ----
    stimulus_functions : process

    variable VLINE : line;
    variable Ain_int : std_logic_vector(3 downto 0);
    variable Bout_int : std_logic_vector(5 downto 0);
    file INVECTOR : TEXT open READ_MODE is "stimulus.txt";

    begin -- process stimulus
    ---------------------------------------------------------------------------
    ----
    -- change signals at negative clock to allow time to settle
    ---------------------------------------------------------------------------
    ----
    Ain(3) <= '1', '0' after half_clk;
    WAIT on Ain(3) until Ain(3) = '0';
    WHILE not(ENDFILE(INVECTOR)) loop
    READLINE(INVECTOR, VLINE);
    READ(VLINE, Ain_int);
    READ(VLINE, Bout_int);
    Ain <= Ain_int;
    wait until rising_edge (Ain(3));
    ASSERT(Bout_int=Bout)
    REPORT "WARNING: Bout is not giving the results as expected"
    SEVERITY WARNING;
    END loop;
    END process;
    END bench;

    ----------------
    The stimulus file is:
    0000
    0001
    0010
    0011
    0101
    ......
    1000
    1001
    ..... so on
    1111

    The second column is the truth-table in the archtitecture shown above.

    Please let me know what am I doing wrong OR what should I write to perform
    the simulation.

    Thank you very much for your help.

    Rajan
     
    rajan, Jul 24, 2003
    #1
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  2. rajan

    Marcin Guest

    Hi Rajan,

    Problem is with : wait until rising_edge (Ain(3));
    in stimulus_functions process.
    You are waiting for rising edge and waiting...

    Regards,
    Marcin

    "rajan" <> wrote in message news:<y7TTa.612846$>...
    > Dear experts,
    >
    > I have made a ROM table in vhdl, and it compiles successfully with Modelsim.
    > But, I am not able to simulate the testbench. What am I doing wrong.
    >
    > -------------------
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.all;
    > use IEEE.STD_LOGIC_ARITH.all;
    > use IEEE.STD_LOGIC_UNSIGNED.all;
    >
    > entity Rom_Table is
    > port(
    > Ain : in std_logic_vector(3 downto 0);
    > Bout : out std_logic_vector(5 downto 0)
    > );
    > end Rom_Table;
    >
    > architecture BEH of Rom_Table is
    > begin
    > process(Ain)
    > constant MEM : NATURAL := 16;
    > type TRUTH_TABLE is array (0 to MEM-1) of std_logic_vector(5 downto
    > 0);
    > constant TABLE : TRUTH_TABLE := (
    > ('0','0','0','0','0','0'),
    > ('0','0','0','0','0','1'),
    > ('0','1','0','0','1','1'),
    > ('1','1','0','0','1','1'),
    > ('0','0','0','0','1','1'),
    > ('0','1','1','1','1','1'),
    > ('0','0','0','0','0','0'),
    > ('0','0','0','0','1','1'),
    > ('0','1','1','0','1','1'),
    > ('1','1','1','0','1','1'),
    > ('0','0','0','0','1','1'),
    > ('0','1','1','1','1','1'),
    > ('1','1','1','1','1','1')
    > ('0','0','0','0','0','0'),
    > ('0','0','0','0','1','1'),
    > ('0','1','1','0','1','1'),
    > );
    >
    > begin
    > Bout <= TABLE(conv_integer(Ain));
    > end process;
    > end BEH;
    > -----------------
    >
    > I have written a TestBench for this as follows. It waits until Ain(3)='1',
    > and then starts giving the output.
    >
    > ------------------------TB------
    > LIBRARY ieee;
    > USE ieee.std_logic_1164.ALL;
    > use std.textio.all;
    > USE ieee.numeric_std.ALL;
    >
    > LIBRARY work;
    > USE work.ALL;
    >
    > ENTITY Rom_Table_tb is
    > END Rom_Table_tb;
    >
    > ARCHITECTURE bench of Rom_Table_tb is
    > COMPONENT Rom_Table PORT ( Ain : IN std_logic_vector (3 DOWNTO 0);
    > Bout : OUT std_logic_vector (5 DOWNTO 0)
    > );
    > END COMPONENT;
    >
    > SIGNAL Ain : std_logic_vector (3 DOWNTO 0);
    > SIGNAL Bout : std_logic_vector (5 DOWNTO 0);
    > SIGNAL half_clk : TIME := 100 NS;
    >
    > BEGIN
    >
    > d1 : Rom_Table PORT MAP (Ain, Bout);
    >
    > ---------------------------------------------------------------------------
    > ----
    > -- Read stimulus from text file "stimulus.txt"
    > ---------------------------------------------------------------------------
    > ----
    > stimulus_functions : process
    >
    > variable VLINE : line;
    > variable Ain_int : std_logic_vector(3 downto 0);
    > variable Bout_int : std_logic_vector(5 downto 0);
    > file INVECTOR : TEXT open READ_MODE is "stimulus.txt";
    >
    > begin -- process stimulus
    > ---------------------------------------------------------------------------
    > ----
    > -- change signals at negative clock to allow time to settle
    > ---------------------------------------------------------------------------
    > ----
    > Ain(3) <= '1', '0' after half_clk;
    > WAIT on Ain(3) until Ain(3) = '0';
    > WHILE not(ENDFILE(INVECTOR)) loop
    > READLINE(INVECTOR, VLINE);
    > READ(VLINE, Ain_int);
    > READ(VLINE, Bout_int);
    > Ain <= Ain_int;
    > wait until rising_edge (Ain(3));
    > ASSERT(Bout_int=Bout)
    > REPORT "WARNING: Bout is not giving the results as expected"
    > SEVERITY WARNING;
    > END loop;
    > END process;
    > END bench;
    >
    > ----------------
    > The stimulus file is:
    > 0000
    > 0001
    > 0010
    > 0011
    > 0101
    > .....
    > 1000
    > 1001
    > .... so on
    > 1111
    >
    > The second column is the truth-table in the archtitecture shown above.
    >
    > Please let me know what am I doing wrong OR what should I write to perform
    > the simulation.
    >
    > Thank you very much for your help.
    >
    > Rajan
     
    Marcin, Jul 29, 2003
    #2
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