To_stdlogicvector

Discussion in 'VHDL' started by ashu, May 12, 2006.

  1. ashu

    ashu Guest

    on comipiling the follwoing prgram i am getting syntax error

    a1 := to_stdlogicvector(a);
    ^
    **Error: /pe_users/guest6/vhdl/adder.vhd line 23
    Syntax error. (VSS-1081)

    am i using to_stdlogicvector function incorrectly ?
    _____________________________________________________________________
    library ieee ;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;
    USE ieee.std_logic_unsigned.all;

    entity adder is

    port (
    a : in bit_vector( 7 downto 0) ;
    b : in bit_vector( 7 downto 0) ;

    sum : out bit_vector(8 downto 0));

    end adder;

    architecture arch of adder is
    variable a1: std_logic_vector(7 downto 0);
    variable b1: std_logic_vector(7 downto 0);
    variable sum1: std_logic_vector(8 downto 0);

    begin -- arch

    a1 := to_stdlogicvector(a);
    b1: = to_stdlogicvector(b);

    sum1:= To_StdLogicVector(a1 + b1);

    sum <= sum1;

    end arch;


    library ieee ;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;
    USE ieee.std_logic_unsigned.all;

    entity adder is

    port (
    a : in bit_vector( 7 downto 0) ;
    b : in bit_vector( 7 downto 0) ;

    sum : out bit_vector(8 downto 0));

    end adder;

    architecture arch of adder is
    variable a1: std_logic_vector(7 downto 0);
    variable b1: std_logic_vector(7 downto 0);
    variable sum1: std_logic_vector(8 downto 0);

    begin -- arch

    a1 := to_stdlogicvector(a);
    b1: = to_stdlogicvector(b);

    sum1:= To_StdLogicVector(a1 + b1);

    sum <= sum1;

    end arch;
     
    ashu, May 12, 2006
    #1
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  2. ashu wrote:


    > a1 := to_stdlogicvector(a);
    > ^
    > **Error: /pe_users/guest6/vhdl/adder.vhd line 23
    > Syntax error. (VSS-1081)
    >
    > am i using to_stdlogicvector function incorrectly ?



    > USE ieee.std_logic_arith.all;
    > USE ieee.std_logic_unsigned.all;


    This is not the reason for your problem, but you should not use them.
    Use Numeric_std instead!


    > begin -- arch
    >
    > a1 := to_stdlogicvector(a);
    > b1: = to_stdlogicvector(b);


    Variables (except shared variables, which is something very special)
    cannot exist outside of processes. Make a1, b1 and the others a signal
    or move them into a process!

    Ralf
     
    Ralf Hildebrandt, May 12, 2006
    #2
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  3. ashu

    ashu Guest

    ralf
    thanks so much
    my problem is that i want to add two 8 bit bit_vectors ...
    and store the result in a 9 bit bit_vector

    now since addtion operation is not defined on two bit vectors ...

    i tried converting them to std_logic and hence had to use this function
    :(

    can u suggest me a another way to add two bit_vectors using + sign ?

    thanks
    ashu
     
    ashu, May 12, 2006
    #3
  4. ashu wrote:


    > my problem is that i want to add two 8 bit bit_vectors ...


    It is strongly recommended to not use bit / bit_vector. The reason:
    There is no 'X' (and all the other driver values) for bit(_vector) you
    cannot see an error if you connect two drivers to one bus.


    > now since addtion operation is not defined on two bit vectors ...
    >
    > i tried converting them to std_logic and hence had to use this function


    std_ulogic(_vector) / std_logic(_vector) has no arithmetics defined,
    because the tool cannot know, if the signal is signed or unsigned. For
    addition there is no difference, but for a comparison it is, because is
    "111" equal to 7 or -1?


    > can u suggest me a another way to add two bit_vectors using + sign ?



    use IEEE.Numeric_std.ALL;

    signal a,b : std_ulogic_vector(15 downto 0);
    signal res : std_ulogic_vector(15 downto 0);

    res<=std_ulogic_vector( unsigned(a) + unsigned(b) );


    You may also declare a,b,res as signed or unsiged to avoid the
    conversions. Another option is to use the type integer.

    Ralf
     
    Ralf Hildebrandt, May 12, 2006
    #4
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