variable sized port map

[sanborne]

Is there a way to have a variable sized port map in VHDL? I am not
talking about using a generic statement to make a variable sized bus,
but I want to have a varying number of inputs as specified by a generic
statement. Is there a way to specifiy an array of standard logic
vectors in the port map, maybe??

Thanks in advance.
S

 

[KJ]

Is this something that you're looking for?

type t_MY_TYPE is std_logic_vector(15 downto 0);
type arr_t_MY_TYPE is array (natural range <>) of t_MY_TYPE;

entity My_Entity is generic(N: natural)
port(Gazintas: in arr_t_MY_TYPE(1 to N);
Gzzoutas: out arr_t_MY_TYPE(1 to N));
end My_Entity;

Here 'Gazinta' and 'Gazouta' are both arrays of 16 bit std_logic_vectors;
You can make an array of anything by first defining a new type and then an
array of that type. The 'base' type t_MY_TYPE could have been an enumerated
list or a record type and the rest of the code would be unchanged. For
example,

type t_MY_TYPE is record
One_Potato: natural range 1 to 50;
Two_Potato: std_logic_vector(7 downto 0);
end record;

KJ

 

[sanborne]

Thankyou very much. That is what I was looking for, and I think it
answers my question.

I am pretty new to VHDL. Is there a good VHDL reference that you would
suggest that has stuff like this? I have questions about the code that
you posted that I think would be best answered on my own if I had a
good book. I have searched the internet quite a bit, and have not found
much more than really basic reference materials. (If you have any good
websites to suggest, I would like that too.)

But for example, why would you use the <> operator in "arr_t_MY_TYPE"
instead of an actual explicit range? And what is a "record" data type
and how is it useful? I should note that I am primarily interested in
synthesizable VHDL. So if you give examples that are only really useful
in testbenches or some other non-synthesizable application, please say
so.

And thanks a lot for your response.

 

[Mike Treseler]

Is there a good VHDL reference that you would
suggest that has stuff like this?

Designer's Guide to VHDL by Ashenden

I have questions about the code that
you posted that I think would be best answered on my own if I had a
good book.

Good examples like KJ's provide focus
and motivation to open a book.
This is a good way to learn.

I have searched the internet quite a bit, and have not found
much more than really basic reference materials. (If you have any good
websites to suggest, I would like that too.)

I like the examples here:
http://home.comcast.net/~mike_treseler/

But for example, why would you use the <> operator in "arr_t_MY_TYPE"
instead of an actual explicit range?

That is an unconstrained range that can
be used on a type *declaration*.
You have to "fill in the box" with
an actual range when you *use* this type.

-- Mike Treseler

 

[Andy]

You really don't have to specify the range until you specify storage
for the data (i.e. declare a signal or variable to hold it). The ports
can be left unconstrained, and will take their widths from the
signal/port they are connected to when they are instantiated. Different
instantiations of the same entity could use different widths. Note
that only the top level array can be left unconstrained in a typedef.
You can have unconstrained arrays of constrained arrays, but not arrays
of unconstrained arrays.

entity My_Entity is
port(Gazintas: in arr_t_MY_TYPE;
Gzzoutas: out arr_t_MY_TYPE);
end My_Entity;

Use Gazintas'range or Gazintas'length in the ensuing architecture to
get the range/length of the port data.

For obvious reasons, you cannot have an unconstrained port on the top
level entity.

Andy

 

[sanborne]

Is there any reason to do this instead of a generic width input for the
array?

S

 

[Mike Treseler]

Is there any reason to do this instead of a generic width input for the
array?

The self-aligning ports might be nice
for a design with many sub-entities using
a common local bus.

A generic width allows a default value:

entity uart is
generic (char_len_c : natural := 8;
tic_per_bit_c : natural := 4);

that can be handy when running a quick
test sim or synthesis of the sub-entity alone.


It doesn't really make much difference.


-- Mike Treseler