VCS- How to use libraries

Discussion in 'VHDL' started by Anil Dalwani, Jun 14, 2004.

  1. Anil Dalwani

    Anil Dalwani Guest

    Hi,

    I was wondering if there is any option to include libraries in vhdl
    design while elaboration with vcs (libraries compiled from vhdl code,
    and libraries are being in vhdl design - I am using scs command for
    elaboration) ?

    The problem is that if I use the "use" clause in my vhdl file , it is
    giving no problem and getting the instance. If I don't have the "use"
    clause in my design then the tool is not scanning the libraries for
    the components and giving warnings in the elaboration that this
    component is not found because it is unbound.

    Is there any option that I need to give on command line with
    elaboration command ?

    Appreciate any help..
    Regards,
    -Anil
    Anil Dalwani, Jun 14, 2004
    #1
    1. Advertising

  2. Hi Anil

    Anil Dalwani wrote:

    >Hi,
    >
    >I was wondering if there is any option to include libraries in vhdl
    >design while elaboration with vcs (libraries compiled from vhdl code,
    >and libraries are being in vhdl design - I am using scs command for
    >elaboration) ?
    >
    >The problem is that if I use the "use" clause in my vhdl file , it is
    >giving no problem and getting the instance. If I don't have the "use"
    >clause in my design then the tool is not scanning the libraries for
    >the components and giving warnings in the elaboration that this
    >component is not found because it is unbound.
    >
    >

    This is the requirement demand by the IEEE 1076.

    If you want that your component are instantiate as black box, you can
    directly define their prototype into the architecture_declarative_part,
    and don't use any 'use'

    >Is there any option that I need to give on command line with
    >elaboration command ?
    >
    >

    If you have compile all your components architecture (before) into work
    library, that is not necessary, because work is implicitly used.

    >Appreciate any help..
    >Regards,
    >-Anil
    >
    >


    JaI
    Just an Illusion, Jun 17, 2004
    #2
    1. Advertising

  3. Anil Dalwani

    priyanka24

    Joined:
    Jan 26, 2012
    Messages:
    4
    vcs simulation problem for vhdl files

    hi..
    i tried to simulate my VHDL code in VCS.
    it executes vhdlan command properly.
    but when i use vcs command it gives following error:
    i have written vcs -debug cnt_bhv
    it gives error as follows
    /usr/bin/ld: cannot find -lncurses
    collect 2: ld returned 1 exit status.

    so simv file is not created and my simv command not executing.
    whats the problem can anybody fix it?
    priyanka24, Feb 19, 2012
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. ©®
    Replies:
    0
    Views:
    385
  2. kartikey
    Replies:
    0
    Views:
    1,542
    kartikey
    Dec 18, 2007
  3. Roedy Green

    VCS hosting?

    Roedy Green, Mar 11, 2008, in forum: Java
    Replies:
    14
    Views:
    790
    Roedy Green
    Mar 12, 2008
  4. priyanka24

    vcs simulation problem

    priyanka24, Feb 19, 2012, in forum: VHDL
    Replies:
    0
    Views:
    803
    priyanka24
    Feb 19, 2012
  5. Skip Montanaro
    Replies:
    0
    Views:
    121
    Skip Montanaro
    Feb 6, 2013
Loading...

Share This Page