VHDL-AMS: assert as simultaneous statement

Discussion in 'VHDL' started by yaveh (Yet Another Vhdl Engineer Hoping), Nov 3, 2006.

  1. Hi,

    I consider good design practise to write case statements with a
    default 'others' choice to be able to catch design errors and
    properly mark them with an assert statement.

    This works fine with VHDL sequentials and concurrent assert statements.

    However, I can´t get VHDL-AMS simultaneous assert statement to work.
    My tool complain with "unknown concurrent/simultaneous statement "
    when I write, e.g.:

    architecture [...] of [...] is
    shared variable a : [...]
    [...]
    begin
    [...]
    case a use
    when a1=> v'dot == -G - v**2*Air_Res; ;-- e.g.
    when b2=> [...]
    when others =>
    assert false report "case defaulted!" severity failure;
    end case;
    end;

    If you use VHDL-AMS, don´t you find it necessary?
    I just can´t find thsi construct in the Quick Reference of several
    VHDL-AMS Simulator...
    yaveh (Yet Another Vhdl Engineer Hoping), Nov 3, 2006
    #1
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  2. yaveh (Yet Another Vhdl Engineer Hoping)

    Paul Floyd Guest

    On 3 Nov 2006 05:32:51 -0800, yaveh (Yet Another Vhdl Engineer Hoping)
    <> wrote:
    >
    > Hi,
    >
    > I consider good design practise to write case statements with a
    > default 'others' choice to be able to catch design errors and
    > properly mark them with an assert statement.
    >
    > This works fine with VHDL sequentials and concurrent assert statements.
    >
    > However, I can´t get VHDL-AMS simultaneous assert statement to work.
    > My tool complain with "unknown concurrent/simultaneous statement "
    > when I write, e.g.:
    >
    > architecture [...] of [...] is
    > shared variable a : [...]
    > [...]
    > begin
    > [...]
    > case a use
    > when a1=> v'dot == -G - v**2*Air_Res; ;-- e.g.
    > when b2=> [...]
    > when others =>
    > assert false report "case defaulted!" severity failure;
    > end case;
    > end;
    >
    > If you use VHDL-AMS, don´t you find it necessary?
    > I just can´t find thsi construct in the Quick Reference of several
    > VHDL-AMS Simulator...


    I haven't checked in the LRM, but I don't think that this is allowed.

    A somewhat ugly solution, which doesn't quite do what you want (but
    might be good enough for simulation), might be to define a function that
    contains an assert.

    For instance

    function my_assert(s: string) return [type of a1, b2 ...] is
    begin
    assert false report s severity failure;
    return 0.0; -- or whatever is compatible with a1 ...
    end;


    case a use
    when a1=> v'dot == -G - v**2*Air_Res; ;-- e.g.
    when b2=> [...]
    when others =>
    dummy == my_assert("case defaulted!");
    end case;

    A bientot
    Paul
    (Not speaking for Mentor Graphics)
    --
    Paul Floyd http://paulf.free.fr (for what it's worth)
    Surgery: ennobled Gerald.
    Paul Floyd, Nov 27, 2006
    #2
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