VHDL automate help, beginner

K

Kleric

Hey

I'm having some problems with my code lock machine.
It is for simulation.

Here is my code:
http://www.box.com/s/129cbfc83b936f275292

It is a lock machine. When the right code is entered it gets opened.
Maybe you could help me to get it working.


The problem is that when i use this line "wait until
rising_edge(clock);" in my lock.vhd file it gives me this error:
Prefixed name 'rising_edge' is not a 1 dimensional array or a function
or contains a bad suffix (index/slice/selected-name)

When I replace this line with this:
wait on clock until clock = '1';
It compiles.
But it doesn't work, my graph stays the same all time.

Thanks
 
G

Gabor

Kleric said:
Hey

I'm having some problems with my code lock machine.
It is for simulation.

Here is my code:
http://www.box.com/s/129cbfc83b936f275292

It is a lock machine. When the right code is entered it gets opened.
Maybe you could help me to get it working.


The problem is that when i use this line "wait until
rising_edge(clock);" in my lock.vhd file it gives me this error:
Prefixed name 'rising_edge' is not a 1 dimensional array or a function
or contains a bad suffix (index/slice/selected-name)
Click to expand...

rising_edge has been around for quite some time, now. What
old software are you trying to compile this with?
When I replace this line with this:
wait on clock until clock = '1';
It compiles.
But it doesn't work, my graph stays the same all time.
Click to expand...

Possibly because this is not the same as rising_edge. You
need to add clock'event to ensure edge dependency like:

wait until clock'event and clock = '1';
Thanks
Click to expand...

If you're writing this code with synthesis in mind, you might want
to use a more standard clocking template like:

process_name: begin
process (clock) begin
if rising_edge(clock) then
case current_state is
when 0 =>
. . .
when others =>
next_state <= 0;
end case;
end if;
end process process_name;

Regards,
Gabor
 
K

Kleric

rising_edge has been around for quite some time, now. What
old software are you trying to compile this with?


Possibly because this is not the same as rising_edge. You
need to add clock'event to ensure edge dependency like:

wait until clock'event and clock = '1';


If you're writing this code with synthesis in mind, you might want
to use a more standard clocking template like:

process_name: begin
process (clock) begin
if rising_edge(clock) then
case current_state is
when 0 =>
. . .
when others =>
next_state <= 0;
end case;
end if;
end process process_name;

Regards,
Gabor
Click to expand...



rising_edge has been around for quite some time, now. What
old software are you trying to compile this with?


Possibly because this is not the same as rising_edge. You
need to add clock'event to ensure edge dependency like:

wait until clock'event and clock = '1';


If you're writing this code with synthesis in mind, you might want
to use a more standard clocking template like:

process_name: begin
process (clock) begin
if rising_edge(clock) then
case current_state is
when 0 =>
. . .
when others =>
next_state <= 0;
end case;
end if;
end process process_name;

Regards,
Gabor
Click to expand...


I'm using Symphony EDA free edition.
Rising_edge still won't work, so the if condition line with:
"if (clock'event and clock='1') then".

Yet the graph doesn't work, it gets stuck.
 
K

Kleric

rising_edge has been around for quite some time, now. What
old software are you trying to compile this with?


Possibly because this is not the same as rising_edge. You
need to add clock'event to ensure edge dependency like:

wait until clock'event and clock = '1';


If you're writing this code with synthesis in mind, you might want
to use a more standard clocking template like:

process_name: begin
process (clock) begin
if rising_edge(clock) then
case current_state is
when 0 =>
. . .
when others =>
next_state <= 0;
end case;
end if;
end process process_name;

Regards,
Gabor
Click to expand...

I'm using Symphony EDA free edition.
Rising_edge still won't work, so I replaced the if condition line with:
"if (clock'event and clock='1') then".

Yet the graph doesn't work, it gets stuck.
 
B

Bart Fox

Am 16.03.12 15:45, schrieb Kleric:
When I replace this line with this:
wait on clock until clock = '1';
It compiles.
But it doesn't work, my graph stays the same all time.
Click to expand...
Your clock is not the problem (but I also prefer the rising_edge function).
Your problem is: You have no point in your code, where current_state is
updated with next_state.

You have a synchronous process. I would suggest to use only one "state"
signal:

entity lock is
port ( reset, clock : in bit;
input : in bit_vector(9 downto 0); -- std_logic_vector is
more common here
output : out bit ); -- std_logic is more common here
end entity;

architecture structure of lock is
signal state: integer range 0 to 8;

begin
process begin
wait until rising_edge(clock);
case state is
when 0 =>
if input = "0000000001" then
state <= 1;
else -- this else path is not really necessary here
state <= 0;
end if;

when 1 =>
-- came "input" from buttons or keys?
-- if yes, you need to synchronize this signal and
-- keep in mind the contact bouncing
if input = "0000000000" then
state <= 2;
else
state<= 0;
end if;
[...]
when 8 =>
state <= 0;
-- no change on putput?
-- how about:
output <= '1';
when others =>
state <= 0;
end case;
end process;
end structure;


regards,
Bart
 
K

Kleric

Am 16.03.12 15:45, schrieb Kleric:
When I replace this line with this:
wait on clock until clock = '1';
It compiles.
But it doesn't work, my graph stays the same all time.
Click to expand...
Your clock is not the problem (but I also prefer the rising_edge function).
Your problem is: You have no point in your code, where current_state is
updated with next_state.

You have a synchronous process. I would suggest to use only one "state"
signal:

entity lock is
port ( reset, clock : in bit;
input : in bit_vector(9 downto 0); -- std_logic_vector is
more common here
output : out bit ); -- std_logic is more common here
end entity;

architecture structure of lock is
signal state: integer range 0 to 8;

begin
process begin
wait until rising_edge(clock);
case state is
when 0 =>
if input = "0000000001" then
state <= 1;
else -- this else path is not really necessary here
state <= 0;
end if;

when 1 =>
-- came "input" from buttons or keys?
-- if yes, you need to synchronize this signal and
-- keep in mind the contact bouncing
if input = "0000000000" then
state <= 2;
else
state<= 0;
end if;
[...]
when 8 =>
state <= 0;
-- no change on putput?
-- how about:
output <= '1';
when others =>
state <= 0;
end case;
end process;
end structure;


regards,
Bart
Click to expand...

I changed my code.
http://www.box.com/s/129cbfc83b936f275292

The graph still stays stuck.
Perhaps it's got to do with the reset variable.
 
A

Anssi Saari

Gabor said:
rising_edge has been around for quite some time, now. What
old software are you trying to compile this with?
Click to expand...

Well, rising_edge is in STD_LOGIC_1164 and takes std_logic as argument.
So he'd need to include that, convert the clock to std_logic and pass it
to rising_edge... Or just make clock std_logic, but then it needs to be
initialized to actually toggle in simulation.

I think the clock'event and clock = '1' route is the simpler route he
should follow at this point.
 
K

Kleric

<snip>

Hi Kleric,
there are a number of issues.

The reason rising_edge doesn't work is that it requires an argument of
std_logic, and you are using bit.

Because you've used integer as your state variable and initialized it to
zero, you have just failed to implement the reset. You should really
implement the reset, as that is applied halfway through the testbench.

But the main problem is that I think you have misunderstood the spec. By
looking at the testbench (which I assume has been provided by your
teacher), it seems that the expected sequence is

1 0 0 8 4 8 6 9

That number represents the bit position in the 10 bit input vector that
is set (IMPORTANT!)

Each state can be held for more than one clock. (IMPORTANT!)

After each "button push", the state returns to all zeros. So this is a
valid sequence on t_input

0000000010
0000000000

00000000001
00000000000

00000000001
00000000000

01000000000
00000000000

00000010000
00000000000

01000000000
00000000000

00001000000
00000000000

10000000000
00000000000

The code represents which bit of the vector is set - you're interpreting
the 10 bit input as an integer, which is wrong.

kind regards
Alan

P.S. Here is another valid sequence

0000000010
0000000000

00000000001
00000000000

00000000001
00000000000

01000000000
00000000000

00000010000
00000000000

01000000000
01000000000 -- no "button release"
00000000000

00001000000
00000000000

10000000000
00000000000
Click to expand...

I had made a mistake in my code, when the case is 2 the input is also 000000000.
But I already use the binary input in my code.
So I have to implement the reset. Where shoul i do that?
as an ifelse block next to the clocking part?
I've been struggling with this code for a while now, every one says different things, the code I have now is a result of this.
 
K

Kleric

Hi Kleric,
for a synchronous reset, you can use

process(Clock)
begin
if clock'event and clock='1' then
if reset = '1' then
-- reset stuff
else
-- normal stuff

end if;
end if;
end process;

For an asynchronous reset use

process(clock, reset)
begin
if reset = '1' then
-- reset stufff
elsif clock'event and clock = '1' then
-- normal stuff

end if;
end process;


regards
Alan

P.S. For synchronous reset, if you like you could also use

process
begin
wait until clock = '1';
if reset = '1' then
-- reset stuff
else
-- normal stuff

end if;
end process;
Click to expand...

Hi, thank you for the help.

http://www.box.com/s/129cbfc83b936f275292

What could the problem be, it still doesn't get anywhere in the graph.

You talked about this
"1 0 0 8 4 8 6 9
That number represents the bit position in the 10 bit input vector that
is set (IMPORTANT!)"

Is there something wrong with my represantion?
if input = "0000000001" then
state <= 2;
 
K

Kleric

Yes, I think there is.

1 means bit position 1, 2 means bit position 2 and so on up to 9 meaning
it position 9. For instance:

9876543210 <-- bit position 1
"0000000010"

Similarly, 6 means
"0001000000" <-- bit position 6

You seem to be coding the value in binary, which of course only uses the
bottom four bits of the 10 bit input vector.

That's why I think 10084869 should be represented as

0000000010 <--1
0000000000 <-- button released
0000000001 0
0000000000 button released
0000000001
0000000000
0100000000
0000000000
0000010000
0000000000
0100000000
0000000000
0001000000
0000000000
1000000000

regards
Alan
Click to expand...


Oh, I get it. They are positions.

Updated
http://www.box.com/s/129cbfc83b936f275292

The graph still doesn't show anything.

Maybe someone could just fix it. I can't figure it out.
I can't change the testbench.
I have used reset, clock, output, input.
Can't find where am I mistaken.
 
E

Enrik Berkhan

Kleric said:
Oh, I get it. They are positions.

Updated
http://www.box.com/s/129cbfc83b936f275292

The graph still doesn't show anything.

Maybe someone could just fix it. I can't figure it out.
I can't change the testbench.
I have used reset, clock, output, input.
Can't find where am I mistaken.
Click to expand...

It runs in ModelSim and the lock actually opens when the mispelled code
number in lock.tb is corrected.

However, your implementation does not require a button to be released
before another one (or even the same one!) is accepted. Further, it will
accept any number of `wrong' buttons pressed in between, AFAICS. Is this
part of the homework spec?

Enrik
 
K

Kleric

It runs in ModelSim and the lock actually opens when the mispelled code
number in lock.tb is corrected.

However, your implementation does not require a button to be released
before another one (or even the same one!) is accepted. Further, it will
accept any number of `wrong' buttons pressed in between, AFAICS. Is this
part of the homework spec?

Enrik
Click to expand...


Sorry, I can't find the error in the lock.tb.
What line if you could say?

The homework spec:
If correct input is entered, then advance to next state.
If wrong input go to the beginning
It has to wait until the previous button is released, after that it can take the next input.

So I must add an else block to every if in the process, to specify what happens, when wrong input is entered. I had this, but I somewhy deleted this.
 
E

Enrik Berkhan

Kleric said:
If anyone could test this. I use Symphony EDA's VHDL simili
Click to expand...

Works for me (free edition). Remember to run the simulation long enough
(e.g. 40 ms).

Enrik
 

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