vhdl code for multiplier in filters

Discussion in 'VHDL' started by sheeja, Mar 5, 2007.

  1. sheeja

    sheeja Guest

    Hi,
    m doing a project on eccm techniques. since the following formulae
    has to be implemented in vhdl n i m not familiar with such vhdl code i
    want help on this.....


    i-8 i-8
    w = ( ∑ vm × va* ) ÷ ( ∑ va × va* )
    k=i k=i

    and Vr = vm – w × va

    where vm and va are arrays consisting of complex nos: which has been
    separated in to real and
    imaginary for the purpose of implementing on fpga.

    can u plz suggest an optimum vhdl code for the above
    formulae...........


    regards
    sheeja
    sheeja, Mar 5, 2007
    #1
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  2. sheeja wrote:
    > Hi,
    > m doing a project on eccm techniques. since the following formulae
    > has to be implemented in vhdl n i m not familiar with such vhdl code i
    > want help on this.....
    >
    >
    > i-8 i-8
    > w = ( ∑ vm × va* ) ÷ ( ∑ va × va* )
    > k=i k=i
    >
    > and Vr = vm – w × va
    >
    > where vm and va are arrays consisting of complex nos: which has been
    > separated in to real and
    > imaginary for the purpose of implementing on fpga.
    >
    > can u plz suggest an optimum vhdl code for the above
    > formulae...........


    I think you should first decide how you want to build this in hardware
    before thinking about the needed VHDL code. What will the frequency be?
    How will you set up the multiplier for real and imaginary parts? Are the
    parts in integers? What FPGA will you place this in, and how much logic
    can be placed between your FFs (pipelining)?

    Also, I'm having trouble understanding your 1st formula. What is i? Why
    does k run from i to i-8? What is indexed by k?

    Kind regards,

    Pieter Hulshoff
    Pieter Hulshoff, Mar 5, 2007
    #2
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  3. sheeja

    Ray Andraka Guest

    sheeja wrote:

    > Hi,
    > m doing a project on eccm techniques. since the following formulae
    > has to be implemented in vhdl n i m not familiar with such vhdl code i
    > want help on this.....
    >
    >
    > i-8 i-8
    > w = ( ∑ vm × va* ) ÷ ( ∑ va × va* )
    > k=i k=i
    >
    > and Vr = vm – w × va
    >
    > where vm and va are arrays consisting of complex nos: which has been
    > separated in to real and
    > imaginary for the purpose of implementing on fpga.
    >
    > can u plz suggest an optimum vhdl code for the above
    > formulae...........
    >
    >
    > regards
    > sheeja
    >


    The real goal here isn't to put this in VHDL, but rather to wind up with
    it in hardware. You could code it in behavioral VHDL and have something
    that is not synthesizable but that is a valid VHDL model.

    With that in mind, your path should start with determining how this will
    map into hardware, only after that is done, then you can start realizing
    that hardware with VHDL. Skipping the hardware visualization step is a
    recipe for failure.

    In order to map the algorithm to hardware, you will first need to
    determine how fast it has to go, how many clocks per sample you have to
    work with, how much precision and dynamic range is required for each
    signal, among other things. You'll also need to ask yourself if this is
    the most efficient way to do this in hardware, and if not what
    alternative algorithms are there. Also, if the x signifies a matrix
    multiply, then you need to break this down into individual complex
    multiplies, and then break that down into the real and imaginary parts
    unless you already have IP blocks that do that for you.

    Finally, if you are not a digital hardware designer, I would strongly
    suggest you employ the services of one who has a background in signal
    processing as well as FPGA design. Without it, you are in for a
    protracted development cycle that doesn't have a high probability of
    success.
    Ray Andraka, Mar 15, 2007
    #3
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