VHDL code PROBLEM ,how to create shift left operation withoutregister in vhdl

Discussion in 'VHDL' started by Wing Chun, Apr 16, 2013.

  1. Wing Chun

    Wing Chun Guest

    Hi!
    I have problem to create shift left operation with 4 bit input to 4bitni output?
    So, I have to create shiftleft component for my ALU but that shifter must have 4bitni input and 4 bit output.
    Does vhdl have some operation for shift ? I try to put sll operation but does not work.
    I also try 4bit input to multiply with 2 but does not work correctly for all combinations.
    I know that component can create with register but that does not work because i have to have 4 bit input and 4 output.
    Wing Chun, Apr 16, 2013
    #1
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  2. Wing Chun

    Guest

    Am Dienstag, 16. April 2013 16:25:32 UTC+2 schrieb Wing Chun:
    > Hi!
    >
    > I have problem to create shift left operation with 4 bit input to 4bitni output?
    >
    > So, I have to create shiftleft component for my ALU but that shifter must have 4bitni input and 4 bit output.
    >
    > Does vhdl have some operation for shift ? I try to put sll operation but does not work.
    >
    > I also try 4bit input to multiply with 2 but does not work correctly for all combinations.
    >
    > I know that component can create with register but that does not work because i have to have 4 bit input and 4 output.


    Hi,
    combinatorical shifting is a simple reassignment of wires.
    e.g.:
    dataout <= datain(2 downto 0) &'0';

    would do a shifting by one and fills up with a zero.
    Rotating is similar:
    dataout <= datain(2 downto 0) & datain (3);

    But please keep in mind not to feedback this stuff, since it would lead to some combinatorical loop (without registers).

    Have a nice synthesis
    Eilert
    , Apr 17, 2013
    #2
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  3. Wing Chun

    valtih1978 Guest

    sll

    Operators in VHDL are type-dependent. Sll is defined for arrays of bits
    and booleans. I am not sure about integer. The standard packages extend
    sll support to the other types.
    valtih1978, Apr 29, 2013
    #3
  4. Re: sll

    Le 29/04/2013 13:04, valtih1978 a écrit :
    > Operators in VHDL are type-dependent. Sll is defined for arrays of bits
    > and booleans. I am not sure about integer. The standard packages extend
    > sll support to the other types.


    Hello
    It doesn't make any sense to define sll for integers in VHDL. Nor for
    booleans, for that matter. In which package is this so ?
    In numeric_std it is defined for signed and unsigned (I think), not
    std_logic_vector

    Niclas
    Nicolas Matringe, Apr 29, 2013
    #4
  5. Re: sll

    Le 29/04/2013 21:29, Nicolas Matringe a écrit :
    > Le 29/04/2013 13:04, valtih1978 a écrit :
    >> Operators in VHDL are type-dependent. Sll is defined for arrays of bits
    >> and booleans. I am not sure about integer. The standard packages extend
    >> sll support to the other types.

    >
    > Hello
    > It doesn't make any sense to define sll for integers in VHDL. Nor for
    > booleans, for that matter. In which package is this so ?
    > In numeric_std it is defined for signed and unsigned (I think), not
    > std_logic_vector


    Ok my bad, it is defined for "arrays of booleans"
    If you want to shift an array of integer you can define your own, thanks
    to operator overloading.

    Nicolas
    Nicolas Matringe, Apr 29, 2013
    #5
  6. Wing Chun

    Andy Guest

    Re: sll

    Numeric_std_unsigned (vhdl-2008) applies the numeric_std-defined operators and functions for unsigned to std_logic_vector. It includes to_integer(slv), and to_slv(natural, size)

    Borrowing a page from SW, shift operations (with zero fill or sign extension) on integers can be implemented by multiplication or division by powers of two. Modulo by power of two may be required with multiplication to control the overall magnitude.

    SLL = (int * 2**n) mod 2**m; -- n = shift bits, m=int bits
    SRL = nat / 2**n;
    SRA = int / 2**n;

    Andy
    Andy, May 1, 2013
    #6
  7. Re: sll

    Le 01/05/2013 15:51, Andy a écrit :
    > Numeric_std_unsigned (vhdl-2008)


    This is heretic ! ;o)

    Nicolas
    Nicolas Matringe, May 1, 2013
    #7
  8. Wing Chun

    Andy Guest

    Re: sll

    I have been using unsigned as my "standard" vector data type for a long time anyway, since it can do anything SLV can, except be compabitle with top level ports on gate level netlists. Numeric_std_unsigned just flips the table the other way. You still need two different types for signed and unsignedarithmetic, so it's not a big deal there either.

    But there are some uses (e.g. one-hot, thermometer, or hamming/ECC encoding), for which the new package would permit an ill-advised numeric interpretation, and reserving SLV for those, and using unsigned/signed for others might makes sense. On the other hand, detecting all zeros by comparing to an integer literal 0 is very user friendly even in those cases.

    YMMV.

    Andy
    Andy, May 2, 2013
    #8
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