I would like to know the vhdl equivalent of verilog trireg.
Depends how much of the Verilog functionality you need to mimic.
The basic behaviour (hold the last driven value, if all drivers
are floated) is easy to achieve: just drive a weaker version
of the signal's level back on to itself, so it holds its value
if all other drivers on it are driving 'Z'. Here's one
possible implementation, using a lookup table as a cut-price
conversion function (one of my favourite pieces of VHDL
testbench trickery):
[in some package]
type sl_map_table is array(std_ulogic) of std_ulogic;
constant weaken: sl_map_table := (
'U' => 'W',
'X' => 'W',
'0' => 'L',
'1' => 'H',
'Z' => 'W',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => 'W'
);
[declaration]
signal my_trireg: std_logic;
[within the architecture]
my_trireg <= weaken(my_trireg);
If I remember correctly, Verilog trireg can also offer a
"capacitive decay" behaviour in which its value collapses
to X if it hasn't been updated after some specified time.
You can imitate this using VHDL inertial delay:
my_trireg <= weaken(my_trireg), 'W' after decay_time;
None of this makes any sense for synthesis, of course.
You also need to be aware that it puts some constraints
on any other logic connected to the same signal:
1) Drivers must drive '1' or '0', never 'H' or 'L',
so that they can overcome the trireg hold value.
2) Any logic that uses the signal's value must
treat 'H' and 'L' as valid '1' and '0' values.
Verilog deals with this automatically. Likewise,
so do all the std_logic_1164 logic operators:
'H' and '1' = '1'
'L' and '1' = '0'
not 'L' = '1'
But you can get into trouble if you test for
'1' or '0' in an "if" or "case", or use
the equality or comparison operators:
if my_trireg = '1' then ...
-- FAILS if my_trireg = 'H' :-(
if my_trireg > '0' then ...
-- SUCCEEDS if my_trireg = 'L' :-(
Most of these problems can be worked-around by
applying the To_X01() strength stripper whenever
you try to make use of the signal value:
if To_X01(my_trireg) = '1' then ...
-- SUCCEEDS if my_trireg = 'H'
Hope this helps.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
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