vhdl & verilog simulation

Discussion in 'VHDL' started by alb, Sep 9, 2013.

  1. alb

    alb Guest

    Hi everyone,

    I sadly found that my Actel Modelsim (10.1b) only supports single
    language simulation (groan!) and I have some verilog modules that I need
    to use in my vhdl testbench. The verilog modules are not synthesizable.

    Any suggestion on how to proceed? I know there are some converters out
    there but wanted to check whether there was any other potential path.

    Thanks,

    Al

    --
    A: Because it fouls the order in which people normally read text.
    Q: Why is top-posting such a bad thing?
    A: Top-posting.
    Q: What is the most annoying thing on usenet and in e-mail?
    alb, Sep 9, 2013
    #1
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  2. alb

    Rob Gaddi Guest

    On Mon, 09 Sep 2013 23:53:57 +0200
    alb <> wrote:

    > Hi everyone,
    >
    > I sadly found that my Actel Modelsim (10.1b) only supports single
    > language simulation (groan!) and I have some verilog modules that I need
    > to use in my vhdl testbench. The verilog modules are not synthesizable.
    >
    > Any suggestion on how to proceed? I know there are some converters out
    > there but wanted to check whether there was any other potential path.
    >
    > Thanks,
    >
    > Al
    >
    > --
    > A: Because it fouls the order in which people normally read text.
    > Q: Why is top-posting such a bad thing?
    > A: Top-posting.
    > Q: What is the most annoying thing on usenet and in e-mail?


    That was when I shelled out for a license for a paid simulator. Aldec
    Active-HDL cost me $2K a year, and has generally been pretty worth it
    versus the free version of ModelSim.

    --
    Rob Gaddi, Highland Technology -- www.highlandtechnology.com
    Email address domain is currently out of order. See above to fix.
    Rob Gaddi, Sep 9, 2013
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  3. alb

    HT-Lab Guest

    On 09/09/2013 22:53, alb wrote:
    > Hi everyone,
    >
    > I sadly found that my Actel Modelsim (10.1b) only supports single
    > language simulation (groan!) and I have some verilog modules that I need
    > to use in my vhdl testbench. The verilog modules are not synthesizable.
    >
    > Any suggestion on how to proceed? I know there are some converters out
    > there but wanted to check whether there was any other potential path.
    >
    > Thanks,
    >
    > Al
    >

    Yes, unfortunately all OEM releases of Modelsim are single language.

    If you don't use any Actel primitives you could try the free Xilinx ISIM
    which is dual language.

    It is a pity your Verilog modules are not synthesizable otherwise you
    could have used a VHDL generated netlist out of Designer (or
    Precision/Synplify). Converters are also out of the game because of this.

    If you are working on a commercial product then I would suggest you bite
    the bullet and get the commercial Modelsim+ version. It will save you a
    lot of hassle. Also, if you look at the price of commercial simulators
    against the cost of an engineer per day it doesn't look so bad any more.
    Remember all prices are negotiable :)

    Good luck,

    Hans.
    www.ht-lab.com
    HT-Lab, Sep 10, 2013
    #3
  4. alb

    alb Guest

    On 10/09/2013 09:25, HT-Lab wrote:
    []
    > If you don't use any Actel primitives you could try the free Xilinx ISIM
    > which is dual language.


    Unfortunately that is not the case, another reason why I hate vendor's
    primitives... (but let me not continue with this rant!)

    > It is a pity your Verilog modules are not synthesizable otherwise you
    > could have used a VHDL generated netlist out of Designer (or
    > Precision/Synplify). Converters are also out of the game because of this.


    This option indeed was also considered, I'm trying to profit of various
    modules written for a verilog testbench which was intended for
    simulation only.

    I was looking specifically for a 1-wire slave model and after some
    search I managed to find it. That said I'm a bit confused about why is
    so complex to make a dual language simulation environment...

    > If you are working on a commercial product then I would suggest you bite
    > the bullet and get the commercial Modelsim+ version. It will save you a
    > lot of hassle. Also, if you look at the price of commercial simulators
    > against the cost of an engineer per day it doesn't look so bad any more.
    > Remember all prices are negotiable :)


    The project is not commercial (it's a scientific payload), but your
    considerations about costs do certainly apply also in this case.
    alb, Sep 10, 2013
    #4
  5. alb

    pini

    Joined:
    Jul 10, 2007
    Messages:
    11
    Location:
    israel
    If the code is not too large better do it manually. It is more readable and easy to maintain. For instance the code of the following SD was converted to VHDL:
    h===://bknpk.no-ip.biz/my_web/SDIO/sd_to_flash_write.html---
    pini, Sep 10, 2013
    #5
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