VHDL JUST FOR ENGINEERS

Discussion in 'VHDL' started by ec, Nov 12, 2006.

  1. ec

    ec Guest

    Hi All

    Is VHDL just for qualified emgimeers ?

    I am a old elect. techition with alot of experince and knowledge.

    I want to get into VHDL based designing.

    What are my theoretical chances ?
    Thanks
    ec
     
    ec, Nov 12, 2006
    #1
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  2. ec

    KJ Guest

    "ec" <> wrote in message
    news:ej7ai4$gcc$...
    > Hi All
    >
    > Is VHDL just for qualified emgimeers ?

    Yes...in the sense that no tool should be in the hands of 'unqualified'
    engineers. But like any other skill it can be learned and mastered. It's
    like learning any other new language, it can be done.

    >
    > I am a old elect. techition with alot of experince and knowledge.

    Presumably boolean logic and some knowledge of how to write software is
    included in that experience.

    >
    > I want to get into VHDL based designing.
    >
    > What are my theoretical chances ?

    Depending on your motivation, 100% is not unreasonable. Good luck in your
    endeavor.

    KJ
     
    KJ, Nov 12, 2006
    #2
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  3. ec

    David Binnie Guest

    Suggest VHDL book by Pedroni is a good start.

    "ec" <> wrote in message
    news:ej7ai4$gcc$...
    > Hi All
    >
    > Is VHDL just for qualified emgimeers ?
    >
    > I am a old elect. techition with alot of experince and knowledge.
    >
    > I want to get into VHDL based designing.
    >
    > What are my theoretical chances ?
    > Thanks
    > ec
    >
    >
     
    David Binnie, Nov 12, 2006
    #3
  4. ec wrote:

    > Hi All
    >
    > Is VHDL just for qualified emgimeers ?
    >
    > I am a old elect. techition with alot of experince and knowledge.
    >
    > I want to get into VHDL based designing.


    My suggestion: start with http://www.vhdl.org/
    Dig into the comp.lang.vhdl FAQ: http://www.vhdl.org/comp.lang.vhdl/
    And start reading this newsgroup on a regular basis.

    > What are my theoretical chances ?


    Theoretically? Why, between 0% and 100 % of course! ;-)
    Practically? Put in a bit of time and perseverance, and 100% should be
    possible.

    --
    Paul.
    www.aimcom.nl
    email address: switch x and s
     
    Paul Uiterlinden, Nov 12, 2006
    #4
  5. ec

    james Guest

    On Sun, 12 Nov 2006 06:19:50 -0800, "ec" <>
    wrote:

    >+++Hi All
    >+++
    >+++Is VHDL just for qualified emgimeers ?
    >+++
    >+++I am a old elect. techition with alot of experince and knowledge.
    >+++
    >+++I want to get into VHDL based designing.
    >+++
    >+++What are my theoretical chances ?
    >+++Thanks
    >+++ec
    >+++

    ***********

    Based on your typing skills, you are going to spend a huge amount of
    time debugging the syntax errors that should abound in your code.

    Other than that a cave man can learn VHDL.


    james
     
    james, Nov 13, 2006
    #5
  6. On Mon, 13 Nov 2006 23:35:02 GMT, james
    <> wrote:

    [...]
    >Other than that a cave man can learn VHDL.


    Ug.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Nov 14, 2006
    #6
  7. ec

    Zara Guest

    On Mon, 13 Nov 2006 23:35:02 GMT, james <> wrote:

    >On Sun, 12 Nov 2006 06:19:50 -0800, "ec" <>
    >wrote:
    >
    >>+++Hi All
    >>+++
    >>+++Is VHDL just for qualified emgimeers ?
    >>+++
    >>+++I am a old elect. techition with alot of experince and knowledge.
    >>+++
    >>+++I want to get into VHDL based designing.
    >>+++
    >>+++What are my theoretical chances ?
    >>+++Thanks
    >>+++ec
    >>+++

    >***********
    >
    >Based on your typing skills, you are going to spend a huge amount of
    >time debugging the syntax errors that should abound in your code.
    >
    >Other than that a cave man can learn VHDL.
    >



    if rising_edge(SUN) then
    if visible(MAMOUTH) then
    hunt(MAMMOUTH);
    eat_as_much_as_you_can();
    else
    hungry<='1';
    end if;
    end if;

    Maybe I should trie to harvest berries to avoid this hungry signal
    being asserted! As soon as copper=(others=>'1') I will start on it.
     
    Zara, Nov 14, 2006
    #7
  8. ec

    Andy Peters Guest

    james wrote:

    > Other than that a cave man can learn VHDL.


    There's a car-insurance commercial in here, somewhere.

    -a
     
    Andy Peters, Nov 15, 2006
    #8
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