vhdl left register

Discussion in 'VHDL' started by CS_, Dec 6, 2009.

  1. CS_

    CS_

    Joined:
    Dec 6, 2009
    Messages:
    3
    can anyone solve this



    Write the VHDL Code for a 16-bit shift left register
    CS_, Dec 6, 2009
    #1
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  2. CS_

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Hi

    Find inspiration in this:

    Code:
    process( clk)
    begin
         if rising_edge( Clk) then
            if reset='1' then
                 Shreg <= (others=>'0');
            else
                 Shreg <= Shreg( 14 downto 0) & Databit;
            end if;
        end if;
    end process;
    jeppe, Dec 6, 2009
    #2
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