Vhdl Ram

Discussion in 'VHDL' started by bmartiniello, Sep 20, 2006.

  1. bmartiniello

    bmartiniello

    Joined:
    Sep 20, 2006
    Messages:
    1
    Hello,

    I am having trouble with a RAM component that I created from a datasheet. The code for the component can be found below. The trouble I am having occurs when I try to write into the memory. If the chip enable (cen) is placed low before the write enable (wen), when the write enable goes low, the input goes undefined. This happens when there is data already in the memory or not. If both cen and wen are placed low at the same time, the write occurs as it should. Any insight as to what causes this problem would be appreciated. Thanks.



    ENTITY mil_11570287_2_1024x4_sram_b IS

    PORT(
    addr : IN std_logic_vector (9 DOWNTO 0);
    cen : IN std_logic;
    wen : IN std_logic;
    I : INOUT std_logic_vector (4 DOWNTO 1)
    );

    END mil_11570287_2_1024x4_sram_b ;


    ARCHITECTURE arch OF mil_11570287_2_1024x4_sram_b IS

    type mem_array is array(0 to 1023) of std_logic_vector(4 downto 1);
    signal sram_values: mem_array;

    BEGIN

    process(cen, wen, I, sram_values, addr)
    begin
    if cen = '0' then
    if wen = '0' then
    sram_values(conv_integer(unsigned(addr))) <= I;
    else
    I <= sram_values(conv_integer(unsigned(addr)));
    end if;
    else
    I <= (others => 'Z');
    end if;
    end process;

    END ARCHITECTURE arch;
    bmartiniello, Sep 20, 2006
    #1
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